PLL Frequency Domain Calibration for PVT-Stable Clock Generation
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Solution Overview
Problem
Phase locked loops (PLLs) face performance degradation due to shifts in the characteristics of digitally controlled oscillators (DCOs) and time to digital converters (TDCs) caused by process, voltage, and temperature variations, leading to noise and frequency distortions.
Innovation Solution
A system utilizing a finite state machine (FSM) and frequency measurement circuit (FMC) for frequency domain calibration and characterization, which measures and compensates for these variations, ensuring stable clock generation by adjusting digital codes and capacitance values in DCOs and TDCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DCO and TDC components are used in PLL to generate high frequency clock, then clock generation capability is improved, but performance shifts occur due to PVT variations causing noise and frequency distortion
Solution Approach 1:
The patent applies preliminary action by performing frequency domain calibration and characterization of DCO and TDC components before actual PLL operation. The system pre-determines the relationship between digital control codes and output frequencies, storing this calibration data for later compensation during normal operation, thereby preventing performance shifts before they occur
Solution Approach 2:
The patent implements feedback by measuring the actual output frequency of the DCO and comparing it with the expected frequency. The system uses this frequency error information to adjust the digital control code, creating a closed-loop compensation mechanism that continuously corrects for PVT-induced performance shifts and maintains stable clock generation
2Reliability
If frequency measurement and calibration operations are performed to compensate for PVT variations, then performance stability is improved, but system complexity increases
Solution Approach 1:
The patent applies self-service by enabling the PLL system to automatically perform its own frequency domain calibration and characterization without requiring external test equipment or manual intervention. The system uses its internal resources to measure, analyze, and compensate for its own performance variations, reducing the need for additional calibration hardware
Solution Approach 2:
The patent implements universality by designing the frequency measurement and calibration functionality to be integrated within the existing PLL structure. The same digital control interface and frequency generation resources are used for both normal operation and calibration operations, allowing the system to perform multiple functions without proportionally increasing hardware complexity
Data Source
AI summary
A system for assigning a characterization and calibrating a parameter is disclosed. The system includes a frequency measurement circuit and a finite state machine. The frequency measurement circuit is configured to measure frequencies of an oscillatory signal and to generate a measurement signal including measured frequencies. The finite state machine is configured to control measurements by the frequency measurement circuit, to assign a characterization to a parameter based on the measurement signal, and to generate a calibration signal based on the characterized parameter.