PLL Frequency Calibration for Stable Locking and Low Phase Noise
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Solution Overview
Problem
Phase-locked loop circuits face issues with output frequency shifting due to process or temperature variations, leading to instability and increased phase noise when the oscillator's frequency exceeds the adjustment range, and increasing the voltage-frequency gain parameter exacerbates this problem.
Innovation Solution
A phase-locked loop circuit with an additional locking loop, magnification adjustment circuit, and frequency calibration circuit to provide fine-tuning control signals, adjusting the oscillator's output frequency to match the target frequency by detecting phase and frequency differences and using control signals to adjust the reference current through multiple magnification levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the voltage-frequency gain parameter (KVCO) of the oscillator is increased to cover a wider range of process and temperature variations, then the oscillator can maintain frequency coverage, but the periodic pulse noise generated when the charge pump charges the filter circuit is amplified, causing more phase noise in the output frequency
Solution Approach 1:
The patent segments the control signal generation into two distinct paths: a first control signal path for fine-tuning frequency within a range, and a second control signal path for coarse frequency adjustment when the first control signal exceeds its adjustment range. This segmentation allows the system to use the appropriate control path based on the magnitude of frequency deviation, thereby avoiding excessive KVCO values that would amplify noise while still covering wide frequency variations.
Solution Approach 2:
The patent implements dynamic switching between two control modes based on the magnitude of frequency deviation. The system dynamically selects whether to use the first control signal (for small deviations) or the second control signal (for large deviations), allowing the KVCO to operate at optimal levels for each scenario and minimizing phase noise while maintaining frequency coverage.
2Adaptability or versatility
If the oscillator frequency shifts beyond the adjustment range of the phase-locked loop, then the phase-locked loop can cover process and temperature variations, but the phase-locked loop circuit will no longer be in a phase-locked state and will be unable to generate a stable output clock signal
Solution Approach 1:
The patent implements dynamic switching between two control modes based on the magnitude of frequency deviation. The system dynamically selects whether to use the first control signal (for small deviations) or the second control signal (for large deviations), allowing the KVCO to operate at optimal levels for each scenario and minimizing phase noise while maintaining frequency coverage.
Solution Approach 2:
The patent employs a feedback mechanism where the phase frequency detection circuit continuously monitors the frequency deviation and provides feedback to determine which control signal path to activate. When the frequency deviation exceeds the first control signal's adjustment range, the feedback triggers the generation of a second control signal with appropriate magnification, ensuring the oscillator remains within the phase-locked range and maintains stable operation.
3Device complexity
If a single control signal path is used for frequency adjustment, then the circuit structure is simple, but the response time to adjust frequency when it shifts beyond the adjustment range is delayed
Solution Approach 1:
The patent segments the control signal generation into two distinct paths: a first control signal path for fine-tuning frequency within a range, and a second control signal path for coarse frequency adjustment when the first control signal exceeds its adjustment range. This segmentation allows the system to use the appropriate control path based on the magnitude of frequency deviation, thereby avoiding excessive KVCO values that would amplify noise while still covering wide frequency variations.
Solution Approach 2:
The patent prepares two control signal paths in advance, with the second control signal path designed to handle large frequency deviations. By having the second control signal path ready and configured with appropriate magnification, the system can quickly respond to large frequency shifts without delay, as the necessary control mechanism is already in place and can be activated immediately when needed.
Data Source
AI summary
A PLL circuit includes a reference current generation circuit, a frequency calibration circuit, a magnification adjustment circuit, an oscillation circuit and a front-end circuit. The frequency calibration circuit generates a current adjustment signal according to a target frequency. The magnification adjustment circuit adjusts a reference current to a target frequency current according to the current adjustment signal. The oscillation circuit generates an output clock signal according to the target frequency current. The front-end circuit detects phase and frequency differences between the output clock signal and a reference clock signal to generate a first control signal. The oscillation circuit adjusts an output frequency to be the same as the target frequency based on the first control signal and the target frequency current. When the first control signal shifts, a second control signal is generated to adjust the target frequency current according to the reference current and the second control signal.