PLL Frequency Holding for Smooth Reference Clock Switching

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Solution Overview

Problem

Traditional phase-locked loop circuits experience significant frequency instability and prolonged re-locking times when the reference clock signal is lost or re-accessed, leading to performance degradation and potential system failure.

Innovation Solution

A phase-locked loop circuit with frequency holding and reference frequency smooth switching, utilizing a capacitor array adjusted by a comparator to maintain a constant control voltage and employing time-to-digital and digital-to-time converters to align clock edges, eliminating the need for re-locking and reducing frequency fluctuations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional phase-locked loop circuit is used when reference clock signal is lost, then the circuit structure is simple, but the output frequency changes greatly affecting loop stability

Engineering Contradiction:

Improveloop stabilityVSAvoidcircuit structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a comparator as an intermediary component that compares the control voltage with a reference voltage and generates a correction signal. This intermediary mechanism prevents direct frequency jumps by mediating the voltage control path, thereby improving loop stability without significantly complicating the overall circuit structure.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements a feedback mechanism where the comparator continuously monitors the control voltage and provides correction signals to maintain it at the reference voltage level. This feedback loop ensures that the VCO frequency remains stable even when the reference clock signal is lost, resolving the contradiction between reliability and complexity.

Inventive Principle:

Principle #23Feedback

2Reliability

If digital-to-analog converter is used to adjust control voltage after reference clock loss, then the control voltage can be kept stable, but large delay causes frequency jumping

Engineering Contradiction:

Improvecontrol voltage stabilityVSAvoidconverter delay

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent replaces the digital-to-analog converter mechanism with a direct analog comparison and correction approach using a comparator. This substitution eliminates the conversion delay inherent in ADC/DAC systems while maintaining control voltage stability, thereby resolving the time loss issue without sacrificing reliability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Productivity

If traditional phase-locked loop circuit is used when reference clock signal is re-accessed, then the circuit structure is simple, but long re-locking time causes output frequency to change constantly

Engineering Contradiction:

Improvere-locking speedVSAvoidcircuit structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent maintains the control voltage at the reference voltage level continuously, even before reference clock re-access occurs. This preliminary preparation ensures that when the reference clock returns, the VCO is already at the correct frequency setting, eliminating the need for lengthy re-locking processes and improving productivity without significant circuit complexity increase.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent uses the comparator to maintain a stable control voltage baseline that cushions against frequency disruptions. This beforehand cushioning ensures that when the reference clock signal is re-accessed, the system is already prepared and stable, preventing constant frequency changes during re-locking while keeping the circuit structure relatively simple.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

4Reliability

If reference clock signal loss is detected and handled traditionally, then the detection mechanism is simple, but output frequency jumps affect circuit performance

Engineering Contradiction:

Improveoutput frequency stabilityVSAvoiddetection and control mechanism

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the frequency stabilization function with the existing reference clock loss detection mechanism by using the same loss detection signal to control the comparator's operation. This merging approach improves output frequency stability during clock loss events without significantly increasing device complexity, as it utilizes existing detection infrastructure.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12184291B1Phase-locked loop circuit with frequency holding and reference frequency smooth switching

Publication Date: 2024.12.31 MAGNICHIP CO LTD

AI summary

A phase-locked loop circuit comprises a clock signal loss detection module, a time-to-digital converter, a digital-to-time converter, a phase discriminator, a charge pump, a loop filter, a comparator, a voltage-controlled oscillator, a frequency divider, a reference voltage generation module and a switch; a capacitor array of the voltage-controlled oscillator is adjusted by using an output of the comparator, so that a control voltage Vctrl of the voltage-controlled oscillator is constantly equal to a reference voltage after a phase-locked loop is locked and does not change along with a change of a PVT condition; after a reference clock signal is lost, the circuit directly adopts the reference voltage as the control voltage of the voltage-controlled oscillator, and after the reference clock signal is re-accessed, an output delay of the digital-to-time converter is adjusted, clock edge alignment of a new reference clock signal and a feedback clock signal is realized.