Phase-Locked Loop Frequency Presetting for Faster Locking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional phase locked loops experience prolonged locking times, especially when the target frequency of the output clock differs significantly from the initial frequency, which is a concern in systems with varying operation frequencies.
Innovation Solution
Incorporating an initial frequency value provider to detect the frequency of the input clock and provide this information to the controller, allowing the phase locked loop to set the initial frequency of the output clock close to the target frequency using an open loop method, followed by a closed loop adjustment to precisely match the frequency, thereby reducing locking time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the phase locked loop starts from a fixed initial frequency and gradually adjusts to the target frequency, then the frequency control is simple, but the locking time becomes excessively long when the target frequency differs significantly from the initial frequency
Solution Approach 1:
The patent applies preliminary action by having the initial frequency value provider detect the input clock frequency and set the output clock's initial frequency close to the target frequency before the phase-locked loop locking process begins. This preliminary frequency setting based on detected input clock characteristics significantly reduces the frequency adjustment range and locking time, while maintaining relatively simple control complexity through automated detection and setting.
2Adaptability or versatility
If the initial frequency of the output clock is set far from the target frequency, then the frequency adjustment range is large providing better adaptability, but the locking time increases significantly
Solution Approach 1:
The patent performs preliminary frequency detection and setting before the locking process. The initial frequency value provider detects the input clock frequency and pre-sets the output clock frequency close to the expected target, thereby reducing the actual adjustment range needed during locking while maintaining adaptability to different input frequencies.
Solution Approach 2:
The patent employs feedback mechanisms where the phase detector continuously compares the output clock frequency with the input clock frequency, and the controller adjusts the output clock based on the phase difference feedback. This feedback loop ensures accurate frequency convergence while the preliminary setting reduces the overall locking time.
Data Source
AI summary
A phase locked loop includes a phase detector configured to compare a phase of an input clock with a phase of a feedback clock to produce a phase comparison result, an initial frequency value provider configured to detect a frequency of the input clock and provide a frequency detection result, a controller configured to generate a frequency control signal based on the phase comparison result and the frequency detection result, and an oscillator configured to generate an output clock in response to the frequency control signal.