PLL Frequency Ratio Detection for Unknown Input Clocks
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Solution Overview
Problem
Current phase-locked loop (PLL) circuits in clock data recovery (CDR) units face challenges in determining a division ratio, especially when the frequency of the input data stream is unknown, limiting their ability to operate over a broad range of frequencies.
Innovation Solution
A system and method within a fractional-N PLL divide control loop calculate the finite resolution, fixed-point frequency ratio between a reference clock and the PLL output frequency, using a frequency synthesizer circuit to enable noise shaping control of a fractional 1/N divider, allowing the PLL to synthesize fractional multiples of the reference frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed integer divider is used in the feedback path, then the PLL can operate at predetermined frequencies, but it cannot adapt to unknown or variable input data stream frequencies
Solution Approach 1:
The patent applies dynamics by transitioning from a static fixed integer divider to a dynamic fractional-N divider that can continuously adjust its division ratio. The divider is controlled by a frequency ratio detector that dynamically determines the appropriate division ratio based on the detected frequency relationship between the reference clock and input data stream, enabling the PLL to adapt to unknown or variable frequencies while maintaining stable operation.
Solution Approach 2:
The patent implements feedback through a frequency ratio detector that continuously monitors the frequency relationship between the reference clock and the input data stream. This feedback mechanism provides real-time information about the frequency ratio, which is then used to adjust the fractional-N divider control, creating a closed-loop system that automatically adapts to frequency changes without external intervention.
2Adaptability or versatility
If a fractional divider is used to achieve fractional multiples of reference frequency, then frequency synthesis flexibility is improved, but determining the correct divisor becomes difficult when output frequency is unknown
Solution Approach 1:
The patent applies preliminary action by using the frequency ratio detector to determine the appropriate division ratio before configuring the fractional-N divider. The detector analyzes the frequency relationship between the reference clock and input data stream in advance, calculates the required division ratio, and then sets the divider accordingly, eliminating the difficulty of determining the correct divisor when the output frequency is unknown.
Solution Approach 2:
The patent replaces the manual or trial-and-error mechanical approach of setting divider ratios with an automated electronic detection and calculation system. The frequency ratio detector electronically measures frequency relationships and computationally determines the appropriate division ratio, substituting complex mechanical adjustment mechanisms with streamlined electronic control.
3Adaptability or versatility
If VCO sweep method is used for frequency acquisition, then the PLL can lock to unknown input frequencies, but the acquisition time is prolonged and complexity increases
Solution Approach 1:
The patent introduces a frequency ratio detector as an intermediary component that directly measures the frequency relationship between the reference clock and input data stream. This intermediary provides immediate frequency ratio information, eliminating the need for time-consuming VCO sweeping and enabling rapid frequency acquisition while maintaining the ability to lock to unknown input frequencies.
Data Source
AI summary
A system and method are provided for determining a frequency ratio in a phase-locked loop (PLL) circuit feedback path. The method accepts a reference signal having a predetermined first frequency and a PLL output signal having a non-predetermined second frequency. The reference signal cycles are counted, creating a first binary count. Likewise, the PLL output signal cycles are counted, creating a second binary count. The second binary count is sampled at an interval responsive to the first binary count, and a right-shifted second binary count is supplied as a ratio of the second frequency divided by the first frequency. More explicitly, the sampling is performed when a first binary count sampling threshold of 2n first frequency cycles is reached. Then, the radix point in the second binary count is shifted n number of radix places to the left.