PLL Frequency Programming for Wireless Spur Mitigation
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Solution Overview
Problem
Wireless communication devices face performance degradation due to spurs generated by digital circuits, which couple with analog circuits, degrading signal quality and making it challenging to integrate analog and digital circuits on the same IC die.
Innovation Solution
Non-uniform frequency programming of PLL settings, including loop bandwidth, frequency equations, frequency division schemes, injection methods, and supply voltages, is used to mitigate spur effects, allowing for optimized performance across different frequency channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If analog and digital circuits are integrated on the same IC die, then device size and cost are reduced, but spur coupling degrades signal quality
Solution Approach 1:
The patent applies local quality by implementing frequency-selective PLL settings that are tailored to specific frequency channels. Different PLL configurations (loop bandwidth, divider ratios, injection methods) are applied locally to different frequency ranges to mitigate spur effects in those specific regions while maintaining integration benefits.
Solution Approach 2:
The patent changes multiple PLL parameters dynamically based on the operating frequency channel. Loop bandwidth, divider ratios, charge pump current, and injection methods are adjusted according to the selected frequency channel to optimize performance and reduce spur coupling for that specific frequency range.
2Object-affected harmful factors
If analog and digital circuits are separated onto different IC dies, then spur coupling is reduced, but device size and cost increase
Solution Approach 1:
The patent converts the harmful effect of integrated spur coupling into a benefit by using the close integration to implement frequency-selective PLL settings. The harmful proximity is transformed into an opportunity to apply targeted mitigation strategies for different frequency channels, turning the integration challenge into a performance optimization feature.
3Device complexity
If uniform PLL settings are used for all frequency channels, then device complexity is reduced, but spur mitigation performance deteriorates
Solution Approach 1:
The patent implements dynamic PLL settings that automatically adjust based on the selected frequency channel. The system transitions from static, uniform settings to dynamic, frequency-adaptive settings, allowing optimal spur mitigation for each channel while maintaining automated operation to limit user-facing complexity.
Solution Approach 2:
The patent creates a universal PLL configuration system that handles multiple frequency channels with different optimal settings through a single integrated controller. The system provides multi-functionality by supporting various loop bandwidths, divider ratios, and injection methods within one PLL structure, eliminating the need for separate circuits for each frequency range.
4Object-affected harmful factors
If frequency-selective PLL settings are implemented, then spur mitigation performance is improved, but device complexity increases
Solution Approach 1:
The patent implements feedback mechanisms where the selected frequency channel information is used to automatically configure the appropriate PLL settings. The system monitors the operating frequency and adjusts loop bandwidth, divider ratios, and injection methods accordingly, providing automated feedback-based optimization without requiring manual intervention.
Data Source
AI summary
Techniques for generating oscillator signals in a wireless communication device are described. A phase-locked loop (PLL) may be used to generate an oscillator signal for a selected frequency channel. Different PLL settings may be used for the blocks in the PLL for different frequency channels. The different PLL settings may be for different PLL loop bandwidths, different amounts of charge pump current, different frequency equations associated with different sets of high and low divider ratios, different frequency division schemes associated with different prescaler ratios and/or different integer divider ratios, high side or low side injection for a super-heterodyne receiver or transmitter, and/or different supply voltages for one or more circuit blocks such as an oscillator. A suitable set of PLL settings may be selected for each frequency channel such that adverse impact due to spurs can be mitigated.