PLL Frequency Step Control for Faster Holdover Pull-In
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Solution Overview
Problem
High-speed communication systems face challenges in maintaining accurate clock signal frequency and phase during transitions, particularly in holdover mode, where the pull-in process is slow due to stringent frequency slope limits, leading to substantial phase build-up and prolonged transition times.
Innovation Solution
A phase-locked loop with a change-limiting loop filter that generates a loop filter output signal based on predetermined frequency and phase slope limits, and introduces a frequency step during transitions to reduce transition time and phase build-up, allowing for gradual frequency changes within specified limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the frequency slope limit is strictly enforced during pull-in process, then the frequency change specification is satisfied, but the pull-in time becomes substantially prolonged and phase build-up increases
Solution Approach 1:
The loop filter dynamically adjusts its operation between two modes: open-loop mode for rapid frequency acquisition and closed-loop mode for precise frequency tracking. This dynamic switching allows the system to satisfy frequency slope specifications while reducing pull-in time by using the appropriate mode at different stages of the pull-in process
Solution Approach 2:
The pull-in process is segmented into two distinct phases: an initial open-loop phase for rapid frequency adjustment and a subsequent closed-loop phase for precise frequency tracking. This segmentation allows the system to optimize performance for each phase separately, achieving both fast pull-in and specification compliance
2Manufacturing precision
If the frequency slope limit is strictly enforced during pull-in process, then the frequency change specification is satisfied, but substantial phase build-up occurs
Solution Approach 1:
The system dynamically switches between open-loop and closed-loop modes to manage phase build-up. During open-loop mode, rapid frequency adjustment occurs with controlled phase changes, and during closed-loop mode, phase errors are corrected through feedback, thereby satisfying frequency specifications while minimizing phase build-up
Solution Approach 2:
The open-loop mode performs preliminary frequency adjustment before transitioning to closed-loop mode. This preliminary action allows the system to get close to the target frequency quickly, reducing the burden on the closed-loop phase and minimizing overall phase build-up
Data Source
AI summary
A method for generating a clock signal by a phase-locked loop includes generating a phase difference signal based on an input clock signal and a feedback clock signal and generating a loop filter output signal. In a first mode, the loop filter output signal is generated based on the phase difference signal and a predetermined frequency slope, and may include generating a phase-slope-limited version of the phase difference signal based on a predetermined phase slope limit and generating a frequency-slope-limited version of the phase difference signal based on the predetermined frequency slope limit. In a second mode, the loop filter output signal may be generated based on the predetermined frequency slope limit, a value of the loop filter output signal, and a target frequency. In the second mode, the loop filter output signal may be generated further based on a predetermined frequency step value.