PLL Frequency Stepping with Delta-Sigma Ramp Control
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Solution Overview
Problem
Phase-locked loops (PLLs) face challenges in rapidly adjusting clock frequencies without causing significant delays, frequency overshoot, or undershoot, and di/dt effects, which can lead to inefficient power management and increased energy consumption in processor systems.
Innovation Solution
The method involves modulating a first frequency division value using a second frequency division value, which can be incremented or decremented by a ramp generator, and employing delta-sigma modulation to smoothly adjust the output clock frequency of a PLL, minimizing delays and frequency deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the output frequency of a PLL is abruptly changed to a new desired frequency, then the frequency adjustment speed is improved, but this causes di/dt effects and frequency overshoot or undershoot
Solution Approach 1:
The frequency adjustment process is segmented into multiple coarse steps rather than a single abrupt change. The PLL frequency is adjusted through intermediate frequencies, dividing the total frequency change into manageable segments that reduce di/dt effects and prevent overshoot/undershoot while maintaining reasonable adjustment speed.
Solution Approach 2:
The system performs preliminary frequency adjustments to coarse-step the PLL frequency close to the desired target frequency before final precise adjustment. This preliminary action reduces the magnitude of the final frequency step, minimizing di/dt effects and improving frequency stability.
2Reliability
If coarse-stepping is used to adjust the PLL frequency, then frequency overshoot and undershoot are reduced, but significant delay occurs in reaching the new desired frequency
Solution Approach 1:
The system uses periodic delta-sigma modulation to dynamically adjust the frequency division value during frequency transitions. This periodic action allows the PLL to smoothly track the desired frequency while maintaining stability, reducing both overshoot/undershoot and adjustment delay compared to traditional coarse-stepping.
Solution Approach 2:
The frequency division value is made dynamic through modulation, allowing continuous adjustment rather than fixed coarse steps. This dynamic approach enables the system to adapt the adjustment rate in real-time, achieving both frequency stability and reduced adjustment delay.
3Productivity
If the processor clock frequency is increased to improve execution speed, then productivity is improved, but power consumption increases proportionally
Solution Approach 1:
The PLL output frequency is dynamically adjusted based on real-time processor workload requirements. The system can rapidly transition between different frequency states using the modulation technique, allowing the processor to operate at high frequencies when needed for productivity while quickly reducing frequency when workload decreases to conserve power.
Solution Approach 2:
The system uses feedback from the processor workload to dynamically control the PLL frequency. This feedback mechanism ensures the processor operates at the optimal frequency for the current task, maximizing productivity when workload is high while minimizing power consumption when workload is low.
Data Source
AI summary
A method and a phase-locked loop (PLL) for generating output clock signals with desired frequencies are described. The PLL is equipped with a ramp generator that increments or decrements a feedback divider value before providing it to a modulator. The modulator modulates the feedback divider value and provides the modulated value to a feedback divider of the PLL for performing frequency division.