PLL Frequency Test Logic for Accurate On-Chip Clock Measurement
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Solution Overview
Problem
The increasing complexity of System-on-Chips (SoCs) with multiple embedded Phase-Locked Loops (PLLs) necessitates new testing architectures to accurately monitor PLL signals without propagating them through device input/output pads, which can lead to inaccurate frequency measurements due to signal allocation and routing issues.
Innovation Solution
Incorporating test logic circuits and a test controller within the PLL system, using standard interfaces like IEEE 1149.1, IEEE 1500, or IEEE 1687, to directly monitor lock signals and clock frequencies, allowing for accurate measurements without routing through IO pads and enabling parallel testing and built-in self-test capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If PLL signals are routed through device IO pads for testing, then external measurement is enabled, but frequency measurement accuracy deteriorates due to signal allocation and routing issues
Solution Approach 1:
The patent extracts the PLL signal monitoring function from the external IO pad routing path and relocates it to internal test logic circuits that directly access the PLL output signal. This extraction eliminates the signal allocation and routing issues that cause measurement inaccuracies while maintaining test capability through internal observation points.
Solution Approach 2:
The patent introduces test logic circuits as intermediary components between the PLL signal source and the measurement function. These intermediary circuits capture and process the PLL output signal internally, serving as a mediator that enables accurate frequency measurement without requiring external IO pad routing and associated signal allocation procedures.
2Productivity
If multiple embedded PLLs are tested using traditional external routing methods, then individual testing is possible, but testing time increases and parallel testing becomes difficult
Solution Approach 1:
The patent segments the testing function by providing dedicated test logic circuits for each embedded PLL, allowing independent and parallel operation of test functions. This segmentation enables multiple PLLs to be tested simultaneously without interfering with each other's signal routing, thereby reducing total testing time while maintaining individual test capability.
Solution Approach 2:
The patent merges the test control functions into a unified test controller that can manage multiple PLL test operations simultaneously. By combining the control logic and utilizing the internal routing infrastructure, the system enables parallel testing of multiple PLLs through a single coordinated controller, improving productivity without requiring separate external routing for each device.
3Measurement precision
If internal test logic circuits are used to monitor PLL signals, then measurement precision improves, but device complexity increases
Solution Approach 1:
The patent implements self-service by enabling the PLL system to monitor and test its own output signals through integrated test logic circuits. The test functions are embedded within the PLL device itself, allowing the system to perform self-diagnosis and self-testing without requiring complex external test equipment or complicated signal routing infrastructure.
Solution Approach 2:
The test logic circuits are designed with multi-functionality to handle various PLL testing requirements through a unified internal structure. By creating a universal test interface that can measure frequency, detect lock status, and monitor signal integrity across different PLL configurations, the patent reduces the need for multiple specialized test circuits, thereby limiting the increase in device complexity.
Data Source
AI summary
A system for testing a circuit includes a phase-locked loop, a test logic circuit, and a test controller. The test logic circuit is coupled to the phase-locked loop. The test logic circuit is configured to count a number of clock cycles of the phase-locked loop using a reference clock as a reference. The reference clock is coupled to the test logic circuit. The test controller is coupled to the phase-locked loop and to the test logic circuit. The test controller is configured to measure a clock frequency of the phase-locked loop with the counted number of clock cycles received from the test logic circuit.