Digital PLL Gain Scheduling for Fast Settling and Low Jitter
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Solution Overview
Problem
Existing digital phase locked loops (PLL) face challenges in achieving fast settling times over wide frequency ranges while maintaining stability and reducing jitter, often requiring impractically high bandwidth.
Innovation Solution
A digital PLL system with a time-to-digital converter, digital loop filter, digitally controlled oscillator, and divider circuit, controlled by a digital control unit that adjusts gain coefficients and N/R values to operate in open- and closed-loop configurations, allowing for dynamic bandwidth adjustment to achieve fast settling without excessive noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If high bandwidth is used to achieve fast settling time, then settling time is reduced, but implementation difficulty increases and performance deteriorates
Solution Approach 1:
The patent applies dynamics by making the loop bandwidth adjustable rather than fixed. The system dynamically changes the loop bandwidth based on operating conditions, allowing it to achieve fast settling when needed while avoiding the implementation difficulties of continuously high bandwidth. This is achieved through a digitally controlled loop filter that can modify its transfer function characteristics.
Solution Approach 2:
The patent changes the parameter of loop bandwidth dynamically. By adjusting the loop bandwidth parameter according to the frequency change magnitude and system state, the system achieves fast settling for large frequency changes while maintaining stability and avoiding excessive noise for smaller changes or steady-state operation.
2Loss of time
If high bandwidth is used to achieve fast settling time, then settling time is reduced, but jitter performance deteriorates
Solution Approach 1:
The system dynamically adjusts loop bandwidth based on the settling phase. During initial settling, higher bandwidth is used to achieve fast response. Once locked, the bandwidth is reduced to minimize jitter and noise, thus resolving the contradiction between fast settling and jitter performance.
Solution Approach 2:
The patent employs periodic or staged action by using different loop bandwidth settings at different phases of operation. The system transitions from a high-bandwidth mode during frequency changes to a low-bandwidth mode during steady-state operation, achieving both fast settling and low jitter at different times as needed.
3Loss of time
If high bandwidth is used to achieve fast settling time, then settling time is reduced, but stability becomes difficult to maintain
Solution Approach 1:
The patent makes the loop characteristics dynamic by adjusting bandwidth based on operating conditions. The system uses high bandwidth temporarily during frequency transitions when fast settling is needed, then switches to lower bandwidth for stable steady-state operation, thus maintaining stability while achieving fast settling when required.
Solution Approach 2:
The system performs preliminary action by pre-adjusting the loop bandwidth and other parameters before and during frequency changes. The digital control unit calculates appropriate loop filter coefficients in advance based on the desired frequency change, ensuring both fast settling and stability are achieved through proactive parameter adjustment.
Data Source
AI summary
In some implementations, a system includes a phase locked loop (PLL) circuit and a digital control unit. The PLL circuit includes a digital loop filter, a digitally controlled oscillator (DCO), and a divider circuit. The digital control unit is configured determine a preset value for the DCO; determine initial gain coefficients and final gain coefficients for the digital loop filter; determine N/R values for the divider circuit; while the PLL circuit is operating in an open-loop configuration, provide the preset value to the DCO, the initial gain coefficients to the digital loop filter, and the N/R values to the divider circuit; after providing the preset value, initial gain coefficients, and N/R values, initiate operation of the PLL circuit in the closed-loop configuration; and in response to detection of a phase lock of the PLL circuit operating in the closed-loop configuration, provide the final gain coefficients to the digital loop filter.