PLL-Gated CDR Circuit for Phase Error Correction
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Solution Overview
Problem
Traditional clock and data recovery (CDR) circuits in optical fiber communication suffer from phase errors due to manufacturing process variations, leading to increased bit error rates (BER).
Innovation Solution
A CDR circuit design incorporating a phase locked loop (PLL) circuit, delay devices, an edge detector, a gated voltage-controlled oscillator, a phase detector, and amplifiers to improve phase alignment and generate a recovery clock and data, with amplifiers adjusting control signals to refine phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional CDR circuit is used, then the device complexity is low, but phase errors occur due to manufacturing process variations leading to increased bit error rate
Solution Approach 1:
The CDR circuit is segmented into multiple functional blocks: a first delay device for delaying input data, an edge detector for generating edge signals, a second delay device for delaying edge signals, a gated voltage-controlled oscillator for generating recovery clock, and a phase detector for detecting phase differences. Each segment performs a specific function to collectively reduce phase errors and bit error rate while managing circuit complexity.
Solution Approach 2:
The phase detector detects phase differences between the first delay signal and the output recovery clock, and this phase information is fed back to control the delay devices and oscillator. This feedback mechanism continuously corrects phase alignment errors, significantly reducing bit error rate by adapting to manufacturing variations and environmental changes.
2Manufacturing precision
If delay devices and phase detectors are added to improve phase alignment, then phase alignment improves, but device complexity increases
Solution Approach 1:
The delay devices are designed with controllable delay amounts that can be dynamically adjusted based on phase detection results. The first delay device delays input data by a first controllable amount, and the second delay device delays edge signals by a second controllable amount. This dynamic adjustment capability enables precise phase alignment while managing circuit complexity through adaptive control rather than fixed complex structures.
Data Source
AI summary
The invention provides a clock and data recovery (CDR) circuit, including a phase locked loop (PLL) circuit, providing a reference voltage; a first delay device, delaying an input data so as to generate a first delay signal; an edge detector, generating an edge signal according to the first delay signal and the input data; a second delay device, delaying the edge signal according to a control signal so as to generate a second delay signal; a first gated voltage-controlled oscillator, generating an output recovery clock according to the second delay signal and the reference voltage; a phase detector, detecting a phase difference between the first delay signal and the output recovery clock so as to generate a phase signal and a output recovery data; and an amplifier, amplifying the phase signal by a factor so as to generate the control signal.