PLL Carrier Tracking Gating for Unstable NFC RF Clocks
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Solution Overview
Problem
In near-field communication (NFC) card emulation mode, phase-lock loop (PLL) circuits in mobile devices face challenges in tracking a reliable radiofrequency (RF) carrier due to amplitude modulation and active load modulation, leading to phase and frequency errors when the RF carrier becomes unreliable.
Innovation Solution
A time-limited gating mechanism is integrated into the PLL circuit, comprising an absolute phase detection sub-circuit, a delay timer sub-circuit, and a pulse gating sub-circuit, which automatically de-asserts phase tracking signals when the signal duration exceeds a threshold, limiting phase and frequency errors during unreliable RF carrier conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the PLL continuously tracks the RF carrier to maintain accurate clock signal generation, then clock accuracy is improved, but phase and frequency errors increase when the RF carrier becomes unreliable due to amplitude modulation and active load modulation
Solution Approach 1:
The system dynamically switches between tracking and non-tracking modes based on the reliability of the RF carrier. The PLL is configured to track the RF carrier when it provides a reliable reference, and to stop tracking when the carrier becomes unreliable due to amplitude modulation and active load modulation. This dynamic adaptation resolves the contradiction by adjusting the tracking behavior according to real-time signal conditions.
Solution Approach 2:
The system employs a feedback mechanism that monitors the reliability of the RF carrier reference and automatically controls the PLL tracking behavior. When the RF carrier becomes unreliable (detected through signal quality assessment), the system provides feedback to stop the PLL from tracking, thereby preventing phase and frequency errors. This feedback loop ensures clock accuracy is maintained while avoiding tracking of unreliable references.
2Reliability
If the PLL stops tracking the RF carrier when it becomes unreliable, then phase and frequency errors are reduced, but time is lost detecting the unreliability and switching modes
Solution Approach 1:
The system performs preliminary assessment of the RF carrier reliability before committing to tracking or non-tracking modes. By continuously monitoring signal quality indicators and having pre-configured tracking control logic, the system is prepared to switch modes rapidly when unreliability is detected, minimizing the time loss associated with mode transitions.
3Duration of action of stationary object
If the PLL tracks the RF carrier during unstable conditions, then continuous clock generation is maintained, but significant phase and frequency drift occurs
Solution Approach 1:
The feedback mechanism continuously monitors RF carrier reliability and automatically controls the PLL tracking state. When instability is detected in the RF carrier, the feedback signal stops the PLL from tracking, preventing phase and frequency drift while maintaining continuous clock generation through the PLL's internal oscillation and memory of the last accurate frequency reference.
Data Source
AI summary
Techniques are described for accurate tracking of a radiofrequency (RF) carrier for amplitude-modulated signals in unstable reference clock environments. For example, some embodiments operate in context of clock circuits in devices configured for near-field communication (NFC) card emulation (CE) mode. The clock circuits seek to generate an internal clocking signal by tracking a clock reference, such as an RF carrier. In some cases, the clock reference can unpredictably become unreliable for periods of time, during which continued tracking of the unreliable clock reference can yield appreciable frequency and phase errors in the generated internal clocking signal. Embodiments implement phase delta detection with time limiting to limit the magnitude of such errors in the internal clocking signal introduced while tracking an unreliable clock reference. For example, embodiments force gating of phase tracking signals to limit their duration, thereby limiting impacts of those phase tracking signals on the clock circuit output.