PLL Gear Shifting With Phase-Error Correction for Fast Locking

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Solution Overview

Problem

Conventional phase-lock loops (PLLs) face challenges in achieving fast locking times and efficient gear shifting, which are crucial for reducing power consumption and enabling quick turn-around times in applications like narrowband Bluetooth Low-Energy (LE) Channel Sounding.

Innovation Solution

The proposed solution involves a phase-lock loop gear shifter that dynamically controls loop gain and uses a gear-shifting module to adjust the loop gain difference and multiply it by a characteristic phase-error value to provide a control-signal correction value, enabling flexible and efficient gear shifting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If conventional PLL gear shifting is used to reduce locking time, then locking speed is improved, but loop phase errors are introduced

Engineering Contradiction:
Improvelocking timeVSAvoidloop phase error
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent applies preliminary action by calculating and storing the control signal correction value before the gear shift occurs. The correction value is computed based on the phase error signal and gain difference, then applied in advance to compensate for the phase error that would otherwise be introduced by the gear shift. This preemptive correction ensures continuous phase alignment during dynamic gear transitions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by continuously monitoring the phase error signal and using it to determine the control signal correction value. The phase error feedback loop dynamically adjusts the correction amount based on current system conditions, ensuring that gear shifts are compensated in real-time. This closed-loop feedback mechanism maintains phase accuracy while enabling fast gear transitions.

Inventive Principle:
Principle #23Feedback

2Productivity

If fast gear shifting is implemented to reduce locking time, then productivity is improved, but phase error disturbances occur

Engineering Contradiction:
Improvelocking speedVSAvoidphase error disturbance
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent introduces an intermediary element - the control signal correction value - that mediates between the gear shift operation and the phase error disturbance. This correction value acts as a buffer that absorbs the disruptive effects of rapid gear changes while allowing the fast gear shifting to proceed. The intermediary correction signal is calculated from the phase error and gain difference, then injected to cancel out the harmful phase disturbances.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Use of energy by moving object

If loop gain is dynamically adjusted for efficient gear shifting, then energy efficiency is improved, but control precision becomes more difficult

Engineering Contradiction:
Improvepower consumptionVSAvoidcontrol precision
Core Design Contradiction:
Use of energy by moving objectVSDifficulty of detecting and measuring

Solution Approach 1:

The patent uses feedback to maintain control precision during dynamic gain adjustment. The phase error signal continuously monitors the system state and feeds back to determine the appropriate control signal correction value. This feedback mechanism ensures that even as the loop gain changes dynamically for energy efficiency, the control precision is maintained through real-time compensation based on actual phase error conditions.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20250055466A1Flexible phase-lock loop gear shifting
Publication Date: 2025.02.13 NXP BV
  • US20250055466A1 patent drawing
  • US20250055466A1 patent drawing
  • US20250055466A1 patent drawing

AI summary

Provided is a phase-lock loop gear shifter that includes: an input for receiving a loop gain that is dynamically controllable; an input for receiving a phase-error signal; a subtractor configured to provide a gain difference between the loop gain input at a second time and the loop gain input at a first time, the first time being earlier than the second time; a module that determines a characteristic phase-error value based on the phase-error signal; and a multiplier that multiplies the gain difference by the characteristic phase-error value to provide a control-signal correction value.