PLL Phase-Frequency Detector With High-Gain Startup Locking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional phase-locked loops (PLLs) face challenges in quickly achieving phase lock during power-up due to stabilization of analog voltages and currents, and their system response is not optimized for power-up mode, leading to prolonged power-up times, especially in data transmission systems where large gain factors are needed but are difficult to achieve without increasing power consumption and parasitic effects.
Innovation Solution
A PLL with a phase-frequency detector (PFD) that includes a mode signal to operate in high-gain or normal modes, where the PFD generates extended pulse widths in high-gain mode to rapidly achieve phase lock by adjusting the PLL output signal frequency, and includes start-up circuitry to assert the high-gain mode briefly during power-up to speed up the phase lock process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PLL operates in normal mode with optimized system response for frequency synthesis, then the PLL provides stable and accurate frequency control, but the power-up time is prolonged due to slow stabilization of analog voltages and currents
Solution Approach 1:
The patent implements a mode signal that dynamically switches the PLL between normal operational mode and high-gain mode. During power-up, the high-gain mode is activated to accelerate phase lock acquisition, and after stabilization, the system transitions to normal mode for accurate frequency control. This dynamic mode switching resolves the contradiction between fast power-up and stable operation.
Solution Approach 2:
The patent changes the gain parameter of the phase-frequency detector based on operational phase. In high-gain mode, the PFD generates extended pulse widths to provide stronger control signals during power-up. In normal mode, the PFD operates with standard gain for precise frequency synthesis. This parameter change allows the system to achieve both fast power-up and stable operation.
2Loss of time
If large gain factors are used to reduce PLL power-up time, then the phase lock acquisition speed increases, but power consumption and parasitic effects increase
Solution Approach 1:
The patent applies high-gain mode periodically or temporarily only during the power-up phase when fast phase lock acquisition is needed. Once the PLL achieves phase lock, the system transitions to normal mode with lower power consumption. This periodic application of high gain resolves the contradiction between fast power-up and low power consumption.
Solution Approach 2:
The patent uses high-gain mode as a preliminary action during power-up to quickly establish phase lock. After the preliminary phase lock is achieved, the system switches to normal mode for sustained operation. This preliminary high-gain action reduces overall power consumption by limiting high-gain operation to only when necessary.
3Use of energy by stationary object
If the PLL is turned off to conserve power during data transmission intervals, then power consumption is reduced, but the PLL must be powered up and achieve phase lock quickly each time data transmission resumes
Solution Approach 1:
The patent implements dynamic mode switching that activates high-gain mode during power-up after the PLL is turned off. This allows the PLL to quickly resume operation when data transmission needs to restart, resolving the contradiction between power conservation and fast resume capability.
4Measurement precision
If conventional PFD pulse widths are used in normal mode, then the PLL provides accurate phase error detection, but the phase lock acquisition time during power-up is prolonged
Solution Approach 1:
The patent changes the pulse width parameter of the PFD outputs based on operational mode. In high-gain mode, the PFD generates extended pulse widths that provide stronger control signals to accelerate phase lock acquisition. In normal mode, the PFD generates standard pulse widths for accurate phase error detection. This parameter change resolves the contradiction between fast acquisition and accurate detection.
Data Source
AI summary
A phase-locked loop (PLL) includes PLL loop circuitry, a frequency divider, and a phase-frequency detector (PFD) that can produce both high-gain output signals to operate the PLL in a high-gain mode and normal output signals to operate the PLL in a normal (not high-gain) mode. A mode signal can be used to switch the PFD between high-gain mode and normal operational mode. When the mode signal indicates high-gain mode, the PFD output signals are extended by one or more additional clock cycles beyond their length when the mode signal indicates normal operational mode.