PLL Holdover Switching for Phase-Aligned Reference Clocks
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Solution Overview
Problem
Phase-locked loops (PLLs) face disruptions and potential loss of lock when switching between redundant reference clocks that are not phase-aligned, leading to instability in clock signals and potential system crashes.
Innovation Solution
Implementing a holdover mode in PLLs that decouples the output from oscillators and uses a multi-mode divider to align the feedback clock with the new reference clock, maintaining a constant frequency and reducing disturbances during switching by adjusting the divisor value in a feedback loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant reference clocks are used to improve reliability, then system reliability is improved, but phase misalignment between oscillators causes PLL disturbances and potential system crashes
Solution Approach 1:
The patent implements a holdover mode that is activated before the actual oscillator switching occurs. In this holdover mode, the PLL output is decoupled from the oscillators and held at a constant frequency while the divider's input N is adjusted in a feedback loop to align the feedback clock with the new reference clock. This preliminary alignment action ensures that when switching occurs, phase disturbances are minimized, thus maintaining system reliability while preventing phase offset problems.
2Duration of action of stationary object
If oscillators are switched to maintain operation, then system continuity is maintained, but phase misalignment causes PLL to lose lock and stop functioning
Solution Approach 1:
Before switching oscillators, the system enters holdover mode where the PLL output is decoupled and held constant while the divider ratio is adjusted to pre-align the feedback clock with the incoming reference clock. This preliminary alignment ensures that when the oscillator switch occurs, the PLL maintains lock stability and continues functioning without interruption.
Solution Approach 2:
The patent employs a feedback loop during holdover mode that continuously monitors the alignment between the feedback clock and the new reference clock, dynamically adjusting the divider's input N to achieve optimal alignment. This feedback mechanism ensures that the PLL maintains stable lock during the transition, preventing loss of lock and ensuring continuous operation.
3Ease of operation
If phase alignment is maintained at all times, then hitless switching is achieved, but additional circuitry increases system complexity
Solution Approach 1:
Instead of maintaining static phase alignment at all times through complex circuitry, the patent implements a dynamic solution where the PLL enters holdover mode temporarily during switching events. In this mode, the divider ratio is dynamically adjusted in a feedback loop to achieve alignment only when needed. This dynamic approach provides hitless switching capability while avoiding the continuous complexity of static alignment circuitry.
Data Source
AI summary
A phase-locked loop (PLL) performs hitless switching from a first reference clock (ref1) to a second reference clock (ref2) by entering holdover mode (418), and aligning the feedback clock (fbclk) to the second reference clock while in holdover mode. The alignment is performed by adjusting a divisor input (D) for the multi-mode divider (128) that divides the output clock frequency (PLLout) to generate the feedback clock. Other features are also provided.