PLL Holdover Circuit With Soft Reacquisition of Phase Lock
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Solution Overview
Problem
Phase-locked loops (PLLs) face challenges in transitioning from holdover mode to reacquiring phase lock, resulting in large transient frequency variations due to uncontrolled tuning voltage changes, which can lead to unacceptable frequency perturbations in output clock signals, particularly in applications with strict timing constraints like cellular infrastructure.
Innovation Solution
A clock system incorporating a PLL, a control circuit, and a holdover circuit connected via a variable resistor, where the control circuit enables a soft transition from holdover to phase lock by incrementally increasing the resistor's resistance, gradually phasing out the holdover circuit's influence on the PLL's loop filter, thereby stabilizing the VCO's tuning voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the holdover circuit is directly connected to the loop filter without a variable resistor, then the circuit structure is simple, but large transient frequency variations occur during transition from holdover to phase lock mode
Solution Approach 1:
A variable resistor is introduced as an intermediary component between the holdover circuit and the loop filter. This resistor acts as a mediator that controls the interaction strength between these two circuits during mode transition, enabling a gradual handover from holdover to phase lock mode and preventing abrupt frequency changes.
Solution Approach 2:
The variable resistor's resistance value is dynamically adjusted during the transition from holdover to phase lock mode. By changing the resistance from a first value to a second value, the system creates a dynamic transition process that smoothly transfers control from the holdover circuit to the phase lock loop, avoiding sudden frequency perturbations.
2Speed
If the variable resistor's resistance is abruptly changed during transition, then the transition speed is fast, but large voltage perturbations occur in the VCO tuning voltage
Solution Approach 1:
The transition process is divided into multiple stages with periodic adjustment of the variable resistor's resistance value. Instead of a single abrupt change, the resistance is adjusted in steps or continuously over time, creating a periodic or progressive transition that maintains voltage stability while achieving mode switching.
Solution Approach 2:
The variable resistor provides a cushioning effect during the transition by gradually reducing the holdover circuit's influence on the loop filter. This beforehand cushioning prevents sudden voltage spikes or drops in the VCO tuning voltage by smoothing the handover process before the complete transition to phase lock mode.
Data Source
AI summary
Provided herein are apparatus and methods for phase-locked loops (PLLs). In certain configurations, a clock system includes a PLL, a control circuit, and a holdover circuit that is electrically coupled to an input of the PLL's loop filter via a holdover switch and a variable resistor. The control circuit generates an input clock signal for the PLL based on a selected reference clock signal. When the control circuit determines that the selected reference clock signal is unreliable, the control circuit disables the PLL's feedback loop and turns on the holdover switch. After the selected reference clock signal is changed or otherwise becomes reliable, the control circuit enables the PLL's feedback loop while keeping the holdover switch turned on, and controls a resistance of the variable resistor over time to provide a soft transition from holdover to reacquiring phase lock.