PLL Hyper Ring Oscillator for Low-Voltage High-Frequency Clocks
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Solution Overview
Problem
Conventional phase locked loops face difficulties in generating higher frequency internal clock signals under low power supply voltage conditions and require a larger chip area due to the need for multiple dividers.
Innovation Solution
A phase locked loop circuit with a voltage controlled oscillator that includes a hyper ring oscillator, directly generating multiple internal clock signals without dividers, allowing for higher frequency clock generation even at low power supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional dividers are used to generate high frequency internal clock signals, then the frequency multiplication capability is improved, but the chip area increases and the circuit complexity increases
Solution Approach 1:
The patent extracts and removes the divider components from the conventional PLL circuit. By using a VCO that directly generates high frequency internal clock signals (ICLK0-ICLK270) without requiring external dividers, the chip area is reduced while maintaining the frequency multiplication capability from 1 GHz external clock to 2 GHz internal clocks.
Solution Approach 2:
The VCO is designed to perform multiple functions: it generates the feedback clock signal (DCLK) for phase comparison and simultaneously generates all four internal clock signals (ICLK0, ICLK90, ICLK180, ICLK270) directly. This multi-functionality eliminates the need for separate divider circuits, reducing both chip area and circuit complexity.
2Speed
If conventional dividers are used to generate high frequency internal clock signals, then the frequency multiplication capability is improved, but the device complexity increases
Solution Approach 1:
The patent removes the complex divider circuitry from the PLL architecture. The VCO directly outputs the required internal clock signals without needing external division logic, significantly simplifying the overall device complexity while achieving the same frequency multiplication effect.
Solution Approach 2:
The VCO is designed as a multi-functional component that simultaneously provides the feedback clock for phase detection and generates all four quadrature internal clock signals. This consolidation of functions into a single component reduces the number of discrete circuits and interconnections, thereby reducing device complexity.
3Speed
If higher frequency internal clock signals are generated using conventional VCO and dividers, then the clock frequency is improved, but the power supply voltage requirement increases
Solution Approach 1:
By removing the divider circuits from the signal path, the patent eliminates the associated power consumption and voltage requirements. The VCO directly generates the high frequency internal clocks, allowing operation at lower power supply voltages (below 2V) while maintaining 2 GHz internal clock frequency capability.
Data Source
AI summary
A phase locked loop circuit and method of locking a phase. The phased locked loop circuit may include a phase detector receiving an external clock signal and a feedback clock signal and outputting an up signal when a phase of the external clock signal leads a phase of the feedback clock signal and outputting a down signal when the phase of the external clock signal lags the phase of the feedback clock signal, a loop filter circuit increasing a control voltage in response to the up signal and decreasing the control voltage in response to the down signal, and a voltage controlled oscillator circuit receiving the control voltage and directly generating at least n (where n is an integer ≧4) internal clock signals. The phased locked loop circuit may also include a voltage controlled oscillator circuit, including at least four loops, receiving the control voltage and generating multiple internal clock signals.