PLL Double Integrator Using Intermittent gm Amplifier for Fast Stable Lock
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Solution Overview
Problem
Conventional PLL circuits face a trade-off between high-speed phase lock and stability, as increasing oscillation frequency leads to increased filter circuit area and mutual conductance, making it difficult to dynamically adjust the zero point for both high-speed lock and stability.
Innovation Solution
A PLL circuit with a double integrator path using an intermittent operation amplifier, where a pulse signal controls the gm amplifier to operate intermittently, reducing mutual conductance and allowing high-frequency oscillation without increasing filter circuit area, by dynamically adjusting the zero point before and after phase lock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the oscillation frequency is increased to achieve high-speed phase lock, then the phase lock speed is improved, but the filter circuit area and mutual conductance increase
Solution Approach 1:
The patent applies periodic action by using an intermittent operation amplifier that operates only during specific phases (coarse adjustment phase and fine adjustment phase) rather than continuously. The amplifier is controlled by a control signal that enables it to function periodically, allowing the PLL circuit to achieve high-speed phase lock while keeping the amplifier non-operational during other periods, thus avoiding continuous increase in mutual conductance and filter circuit area requirements.
2Area of stationary object
If the mutual conductance gm is reduced to decrease filter circuit area, then the filter circuit area is reduced, but the circuit operation becomes abnormal
Solution Approach 1:
The patent implements dynamics by making the amplifier operation intermittent rather than static and continuous. The amplifier's operation state is dynamically controlled by a control signal that switches it between operational and non-operational states. This dynamic control allows the circuit to maintain normal operation during required phases while reducing the effective mutual conductance over time, thereby decreasing filter circuit area without sacrificing reliability.
3Speed
If the zero point is arranged at high frequency for high-speed phase lock, then the phase lock speed is improved, but the circuit stability deteriorates
Solution Approach 1:
The patent uses periodic action to dynamically adjust the zero point position through intermittent amplifier operation. During coarse adjustment phase, the amplifier operates to position the zero point at high frequency for fast phase lock. During fine adjustment phase, the amplifier operates again to reposition the zero point at low frequency for stability. This periodic switching of amplifier states enables the zero point to be dynamically relocated between high and low frequencies, resolving the contradiction between speed and stability.
Data Source
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AI summary
A PLL circuit includes a phase comparator, an integrator path, a proportional path, a current controlled oscillator, a divider, and a double integrator path. The double integrator path includes an intermittent operation gm amplifier, a filter circuit, and a voltage-current conversion circuit. The intermittent operation gm amplifier receives an output voltage of a filter circuit. When a pulse CLK for an intermittent operation is ON, the intermittent operation gm amplifier outputs its voltage to the filter circuit. When the pulse CLK for the intermittent operation is OFF, the intermittent operation gm amplifier does not output the output voltage of the filter circuit to the filter circuit. Even when the pulse CLK for the intermittent operation is OFF, an input potential of the voltage-current conversion circuit is held by the filter circuit, and a current to the current controlled oscillator flows. This makes it possible to oscillate at a high frequency without increasing an area of the filter circuit.