Sub-Sampling PLL Interpolation for Low-Noise Fractional-N Locking
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Solution Overview
Problem
Conventional sub-sampling phase-locked loops (SS-PLLs) face limitations due to the limited resolution of digital-to-time converters (DTCs), leading to spectral degradation and increased phase noise and spurious tones, as they can only operate at integer-N frequencies and have a small lock range.
Innovation Solution
The implementation of a sub-sampling phase-locked loop that includes a digital-to-time converter providing two delay signals, a sampler module, and an interpolator to calculate the ideal sampling instant by interpolating between two samples, thereby increasing spectral purity without the need to enhance DTC resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of the digital-to-time converter is increased to reduce quantization error and improve spectral purity, then spectral degradation and spurious tones are reduced, but device complexity and implementation difficulty increase
Solution Approach 1:
The patent introduces an intermediary mechanism (the interpolator and dual-sampler system) between the coarse DTC and the VCO sampling process. Instead of directly increasing DTC resolution, the system uses two lower-resolution samples taken at different times (t1 and t2) and interpolates between them to achieve the effect of a high-resolution sample at the ideal sampling instant. This mediator approach achieves high spectral purity without requiring a complex high-resolution DTC.
Solution Approach 2:
The patent transitions from a single-time-point sampling approach to a two-dimensional approach by sampling at two different time points (t1 and t2) around the ideal sampling instant. The interpolator then processes these two samples to reconstruct the ideal sampling value. This dimensional change from one time point to two time points allows achieving high precision without increasing the resolution of the original DTC.
2Measurement precision
If a single high-resolution sampling point is used to achieve ideal spectral purity, then measurement precision is maximized, but device complexity increases compared to using multiple lower-resolution samples
Solution Approach 1:
The patent segments the single high-resolution sampling task into two separate lower-resolution sampling operations. Instead of one complex high-resolution sampler, the system uses two simpler samplers operating at slightly different time points. Each sampler has reduced complexity, but together with the interpolator, they achieve the equivalent precision of a single high-resolution sampler.
Solution Approach 2:
The system performs partial sampling actions at two different time points (t1 and t2) that bracket the ideal sampling instant. By taking samples slightly before and after the ideal point and interpolating, the system achieves the precise measurement without requiring any single sampler to have full high-resolution capability. The excessive action of sampling twice compensates for the reduced resolution of each individual sample.
Data Source
AI summary
A sub-sampling phase-locked loop is described, which comprises a digital-to-time converter, a sampler module, an interpolator, and a voltage controlled oscillator. The digital-to-time converter is configured to provide a first delay signal SDLY1 at a first point t1 in time and a second delay signal SDLY2 at a second point in time t2. The sampler module is configured to provide a first sample S1 of the oscillator output signal SOUT at the first point in time t1 and a second sample S2 of the oscillator output signal SOUT at the second point in time t2. The interpolator is configured to provide a sampler signal SSAMPL by interpolating the first sample S1 and the second sample S2. The voltage controlled oscillator is configured to control the oscillator output signal SOUT based on the sampler signal SSAMPL.