PLL Jitter Compensation Using a ΣΔ-Controlled Delay Line
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Solution Overview
Problem
Existing phase locked loop frequency synthesizers face challenges with high out-of-band noise due to frequency division circuits, especially when switching between different frequencies, which is exacerbated by phase detector non-linearities and requires complex compensation methods involving analog-digital conversions.
Innovation Solution
Implementing a variable delay circuitry controlled by a ΣΔ modulator to compensate for jitter before phase detection, utilizing a multi-stage tapped delay line that can be either analog or digital, allowing for precise control of signal timing to reduce noise prior to phase detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a frequency divider switches between different divisors to achieve flexible frequency synthesis, then adaptability is improved, but out-of-band noise increases
Solution Approach 1:
The patent applies preliminary action by compensating for jitter in the reference clock signal before it enters the frequency divider. The variable delay line adjusts the phase of the reference clock signal in advance, preventing jitter from being amplified by the frequency division process, thus reducing out-of-band noise while maintaining frequency flexibility
2Object-generated harmful factors
If jitter compensation is applied after phase detection, then phase noise is reduced, but device complexity increases due to analog-digital conversions
Solution Approach 1:
The patent moves jitter compensation to occur before phase detection by adjusting the reference clock signal phase in advance. This preliminary compensation avoids the need for complex post-detection compensation circuits that would require analog-digital conversions, thereby reducing device complexity while effectively lowering phase noise
Solution Approach 2:
The patent introduces a variable delay line as an intermediary element that directly adjusts the reference clock signal phase. This intermediary approach simplifies the compensation mechanism by using a straightforward delay adjustment rather than complex feedback circuits with analog-digital conversions, reducing overall device complexity
Data Source
AI summary
A phase locked loop frequency synthesizer with jitter compensation having a tapped delay line for compensating the jitter prior to passing a signal subject to jitter through a non-linearity; and, a ΣΔ modulator for generating, or a storing element for pre-generated storing, of a fractional pattern representing fractional weighting of a plurality of integer divisors, wherein the fractional pattern identifies one integer divisor, out of the plurality of integer divisors, at a time to be active.