Phase-Locked Loop Jitter Mitigation for Gapped Signals
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Solution Overview
Problem
Conventional Phase Locked Loops (PLLs) used in frequency synthesis for gapped signals have limited bandwidth, which restricts their jitter attenuation efficiency, making them unsuitable for many applications, especially in Optical Transport Networks where precise synchronization is required.
Innovation Solution
A phase mitigation module is integrated into the PLL to generate discrete correction values that offset phase errors between the input signal with jitter and the feedback signal, allowing for effective jitter mitigation without limiting the PLL bandwidth, by ensuring the average correction values are zero and do not affect PLL performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PLL bandwidth is reduced to attenuate jitter from the gapped signal, then jitter attenuation is improved, but the PLL application versatility and response capability are limited
Solution Approach 1:
The invention segments the jitter attenuation function from the PLL bandwidth control. A dedicated phase mitigation module processes phase errors separately from the main PLL loop, allowing the PLL to operate at high bandwidth while jitter is removed through the separate correction path. The phase detector output is divided into: (1) a corrected path through the phase mitigation module that removes jitter, and (2) a direct path that maintains high bandwidth response.
Solution Approach 2:
The phase mitigation module acts as an intermediary between the phase detector and the DCO. It processes the phase error signal by generating correction values that are added to the PFD output, mediating the jitter removal without limiting the overall PLL bandwidth. This intermediary structure allows high-frequency jitter components to be filtered while preserving the PLL's ability to respond to legitimate frequency changes.
2Reliability
If the PLL bandwidth is reduced to remove jitter, then jitter removal effectiveness is improved, but the signal synchronization speed deteriorates
Solution Approach 1:
The phase error signal is segmented into different frequency components that are handled separately. The phase mitigation module specifically targets and removes high-frequency jitter components while allowing low-frequency synchronization signals to pass through unaffected. This segmentation enables simultaneous high-speed synchronization and effective jitter removal.
Solution Approach 2:
The invention implements a feedback mechanism where the phase mitigation module continuously monitors the phase error and generates correction values in real-time. The correction values are fed back to the DCO to compensate for jitter, creating a closed-loop system that maintains both high bandwidth response and effective jitter removal. The feedback ensures that synchronization speed is not compromised while achieving the desired jitter attenuation.
3Reliability
If conventional PLL with low bandwidth is used, then jitter attenuation is achieved, but the circuit complexity increases due to additional components
Solution Approach 1:
The phase mitigation module is merged with the existing PLL structure, sharing common components such as the phase detector, loop filter, and DCO. The correction value generator is integrated into the feedback path, utilizing the existing phase error signal without requiring a separate jitter removal circuit. This merging approach achieves effective jitter attenuation while minimizing additional circuit complexity.
Data Source
AI summary
Systems and methods for efficient jitter mitigation or removal from a gapped signal. A phase mitigation module is employed to generate discrete correction values for modifying phase error signals detected between a gapped signal and a feedback signal of the PLL. The correction values can be digitally subtracted from the output of a phase frequency detector associated with the PLL. The sequence of correction values can be determined based on phase frequency differences between the input signal and a targeted feedback signal that is free of jitter and has a period equal to an average period of the input signal. An average of the correction values is substantially equal to zero, and an average of the modified phase error signal is substantially equal to zero.