PLL Clock Jitter Masking for Deterministic Jitter Suppression
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Solution Overview
Problem
Existing clock generation methods, such as those using multiplying delay locked loops (MDLL) and phase lock loops (PLL), face a tradeoff between suppressing deterministic jitter and introducing random jitter, with current solutions being complex and inefficient.
Innovation Solution
An apparatus comprising a phase detector, a mask circuit, a loop filter, and a controlled oscillator that detects timing differences between input and output clocks, masks phase error signals based on a deterministic jitter indicator, and generates an oscillator control signal to adjust the output clock, effectively disregarding pre-known deterministic jitter while minimizing random jitter introduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a PLL is used with a smaller bandwidth to suppress deterministic jitter of the input clock, then the deterministic jitter of the output clock is reduced, but the random jitter of the output clock increases
Solution Approach 1:
The phase error signal is segmented into deterministic jitter components and random jitter components. The mask circuit identifies and masks the deterministic jitter portions based on the deterministic jitter indicator signal, allowing separate handling of different jitter types. This segmentation enables suppression of deterministic jitter without unnecessarily filtering random jitter components.
Solution Approach 2:
The masking operation applies local quality control to specific portions of the phase error signal. Instead of uniformly filtering all phase errors, the mask circuit selectively masks only those phase errors corresponding to deterministic jitter events, preserving the quality of random jitter components while eliminating deterministic patterns.
2Reliability
If a PLL is used with a larger bandwidth to reduce random jitter of the output clock, then the random jitter is reduced, but the deterministic jitter of the output clock increases
Solution Approach 1:
The phase error signal is segmented into deterministic jitter components and random jitter components. The mask circuit identifies and masks the deterministic jitter portions based on the deterministic jitter indicator signal, allowing separate handling of different jitter types. This segmentation enables suppression of deterministic jitter without unnecessarily filtering random jitter components.
Solution Approach 2:
The masking operation applies local quality control to specific portions of the phase error signal. Instead of uniformly filtering all phase errors, the mask circuit selectively masks only those phase errors corresponding to deterministic jitter events, preserving the quality of random jitter components while eliminating deterministic patterns.
3Manufacturing precision
If conventional methods are used to reduce deterministic jitter, then the deterministic jitter is reduced, but the circuit complexity increases
Solution Approach 1:
The mask circuit merges the deterministic jitter indicator signal with the phase error signal through a logical masking operation. This combining approach integrates deterministic jitter suppression functionality into the existing PLL structure without requiring separate complex suppression circuits, thereby reducing overall circuit complexity while maintaining effectiveness.
Data Source
AI summary
A method for generating an output clock comprising: detecting a timing difference between a first input clock and a second input clock to generate a phase error signal; generating a masked phase error signal by masking the phase error signal based on a deterministic jitter indicator signal; generating an oscillator control signal by filtering the masked phase error signal; and generating the output clock in accordance with the oscillator control signal.