PLL Jitter Detection via Phase Comparator Metastability
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Solution Overview
Problem
Existing technologies struggle to effectively detect jitter in phase locked loop (PLL) circuits, particularly in safety-critical applications like automotive systems, which can lead to data corruption and safety hazards due to factors such as single event upsets, ground bounce, and electromagnetic interference, necessitating continuous supervision to meet stringent safety standards.
Innovation Solution
A PLL circuit and method incorporating a phase comparison module with a flip-flop phase comparator, synchronizer, and measurement module to detect metastable outputs and measure metastability resolution time, providing an output indicative of jitter based on the time taken for the phase comparator to settle after a change in clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional PFD output monitoring is used for PLL BIST, then frequency detection capability is provided, but metastable-induced errors cause incorrect control assertions over the VCO
Solution Approach 1:
The patent extracts the metastability detection function from the conventional PFD output monitoring by adding a dedicated measurement module that specifically monitors metastable states. This separate measurement path allows detection of metastable conditions without interfering with the normal frequency detection function, thereby preventing incorrect VCO control assertions while maintaining frequency detection capability.
Solution Approach 2:
The patent introduces an intermediary measurement module that acts as a mediator between the PFD output and the VCO control logic. This intermediary detects metastable states and provides information to prevent incorrect control assertions, while the normal frequency detection path continues to operate independently for its intended function.
2Reliability
If continuous supervision of safety-critical parameters is implemented, then safety requirements are met, but system complexity and resource consumption increase
Solution Approach 1:
The patent merges the jitter detection function with the existing PLL BIST infrastructure by utilizing the phase comparison module and loop filter that already exist in the PLL circuit. The measurement module is integrated into this existing structure, allowing safety-critical parameter supervision without adding completely separate supervision systems, thereby reducing overall complexity.
Solution Approach 2:
The phase comparison module serves multiple functions: it performs normal frequency/phase detection for PLL operation and simultaneously enables jitter detection for safety monitoring. This multi-functionality allows the same hardware to fulfill both operational and safety supervision requirements, reducing the need for dedicated supervision hardware.
3Adaptability or versatility
If the feedback divider operates as a fractional-N divider for normal operation, then frequency flexibility is improved, but jitter measurement accuracy deteriorates due to non-integer division effects
Solution Approach 1:
The patent implements dynamic switching of the feedback divider mode based on operational requirements. During normal operation, the divider operates as a fractional-N divider to provide frequency flexibility. During test mode, it switches to integer divider operation to enable accurate jitter measurement, thus adapting its behavior to the current operational context.
Solution Approach 2:
The patent employs periodic switching between fractional-N and integer divider modes. The system alternates between normal operation with fractional-N division and test operation with integer division, allowing both frequency flexibility and measurement accuracy to be achieved at different time periods without compromising either function permanently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable detection of jitter in PLLs, particularly in safety-critical applications, by measuring metastability resolution time, which correlates with jitter levels, ensuring compliance with safety standards and preventing data corruption.
Implementation Method 1
detect a metastable output in the output signal from the phase comparator over active clock cycles of the application and feedback clock signals
Data Source
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AI summary
The disclosure relates to detecting jitter in phase locked loop (PLL) circuits. Embodiments disclosed include a phase-locked loop, PLL (500) comprising: a phase comparison module (201); a loop filter (102); a voltage controller oscillator, VCO (103); a feedback divider (104); and a jitter evaluation module (502), the phase comparison module (201) comprising a phase comparator (202) and a measurement module (204) configured to detect a metastable output in the phase comparator (202) over active clock cycles of application and feedback clock signals (105, 106) input to the phase comparison module (201) and provide an output signal (208) to the jitter evaluation module (502) indicating a metastability resolution time for the phase comparator (202), the jitter evaluation module (210) being configured to provide an output indicative of jitter based on the metastability resolution time.