On-Chip PLL Jitter Measurement for Cycle-to-Cycle Timing Analysis
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Solution Overview
Problem
Measuring Phase Lock Loop (PLL) jitter in assembled machines and customer environments is challenging due to the need for high-speed oscilloscopes and lab settings, making it difficult to assess during normal operation.
Innovation Solution
An on-chip circuit is integrated into the PLL to measure the delay between reference and feedback clocks cycle by cycle, enabling cycle-to-cycle jitter measurement and long-term jitter analysis during normal system operation in any environment using logic and delay elements like active inverters or LC delay lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional lab equipment (high-speed oscilloscopes) is used to measure PLL jitter, then measurement precision is improved, but device complexity and ease of operation worsen due to requiring specialized lab environments and equipment
Solution Approach 1:
The patent merges the jitter measurement function with the existing PLL circuit by integrating delay elements, latches, and analysis logic directly into the PLL chip. This consolidation eliminates the need for external high-speed oscilloscopes and lab equipment, reducing device complexity while maintaining measurement precision through on-chip cycle-by-cycle delay measurement between reference and feedback clocks
Solution Approach 2:
The PLL circuit performs self-measurement of its own jitter characteristics through integrated on-chip measurement circuitry. The delay elements measure the phase difference between reference and feedback clocks internally, and the analysis logic processes this data without requiring external measurement equipment, enabling the system to self-diagnose timing performance
2Adaptability or versatility
If traditional lab environment measurement is used, then measurement conditions are controlled, but adaptability worsens due to inability to measure in customer environments or during normal operation
Solution Approach 1:
The on-chip measurement circuit is designed to function universally across different environments and operating conditions. It measures jitter during normal PLL operation without requiring specialized lab setups, enabling the same measurement system to operate in manufacturing, field deployment, and customer environments while maintaining measurement capability through environmental adaptation
3Ease of operation
If on-chip measurement circuit is added to PLL, then ease of operation improves by enabling measurement during normal operation, but device complexity increases due to additional on-chip components
Solution Approach 1:
The measurement function is merged with the PLL circuit operations, using the existing clock signals (reference and feedback clocks) that are already present in the PLL. The delay elements sample these existing signals, and the latches capture the phase difference information, allowing jitter measurement to be performed using already-available circuit resources rather than adding completely separate measurement infrastructure
Solution Approach 2:
The measurement circuit uses a limited number of delay elements (e.g., 4 stages) to achieve sufficient measurement resolution for practical jitter assessment. Rather than implementing a full-precision measurement system, the patent applies partial action by using just enough measurement stages to capture cycle-by-cycle jitter variations, balancing measurement capability with circuit complexity
Data Source
AI summary
A jitter measurement circuit and method having an input for receiving a reference signal whose jitter is to be measured, an input for receiving a clock signal having a series of cycles, and a measurement circuit for measuring the delay between the reference signal and the clock signal on a cycle by cycle bases, giving a cycle to cycle jitter measurement. The measurement circuit includes a plurality of n stages, each stage having a delay element including an input. The second and later delay elements have their inputs connected to the output of the previous stage and the first delay element has an input for receiving the reference signal. One of n latches is connected to the input of a corresponding one of the delay elements. Each latch has a clock input for receiving the clock signal, and an output for latching the value on the latches input when the clock input is clocked by an edge of the clock signal. An analysis logic circuit is provided having a plurality of n inputs connected to the outputs of the latches. The analysis logic circuit analyzes the values on the latches to give a measure of jitter.