PLL Loop Filter DC Level Shift for High PSRR at Low Supply Voltage
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Solution Overview
Problem
Low supply voltage applications face challenges with phase-locked loop (PLL) circuits due to the inability of N-channel metal-oxide-semiconductor field-effect transistor (NMOS) source followers to operate effectively, resulting in a low all-band power supply rejection ratio (PSRR) issue.
Innovation Solution
Incorporating a direct current (DC) level shift circuit within the loop filter of the PLL circuit, utilizing an active loop filter with operational amplifiers and capacitors, and employing a charge pumping technique to ensure the NMOS source follower can operate under low supply voltage by adjusting the control voltage to the required level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an NMOS source follower is used in the VCO to achieve high all-band PSRR, then the power supply rejection ratio is improved, but the circuit cannot operate under low supply voltage conditions
Solution Approach 1:
The patent introduces a DC level shift circuit as an intermediary component between the charge pump and the NMOS source follower. This level shift circuit adds a DC offset voltage to the control signal, ensuring that the NMOS transistor receives sufficient gate voltage to operate properly even when the supply voltage is low. The intermediary DC level shift enables the NMOS source follower to maintain high PSRR while operating in low-voltage environments.
2Use of energy by moving object
If the supply voltage is reduced to achieve low power consumption, then the power consumption is reduced, but the NMOS source follower cannot operate normally
Solution Approach 1:
The patent changes the voltage parameter of the control signal by introducing a DC level shift. The DC offset voltage is dynamically adjusted based on the supply voltage level, ensuring that the gate-source voltage of the NMOS transistor remains above the threshold voltage required for proper operation. This parameter change allows the circuit to maintain reliable NMOS operation across different supply voltage levels while consuming low power.
3Ease of operation
If a DC level shift circuit is added to enable low voltage operation, then the operability under low supply voltage is improved, but the circuit complexity increases
Solution Approach 1:
The patent merges the DC level shift function with the existing loop filter circuit. The DC offset generation is integrated into the charge pump output stage, sharing common components such as capacitors and switches with the existing phase-locked loop architecture. This merging approach adds the necessary DC level shifting capability while minimizing the increase in overall circuit complexity by reusing existing circuit elements.
Data Source
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AI summary
A filter includes a filter circuit, a first processing circuit, and a second processing circuit. The filter circuit receives an input signal from an input node of the filter, and converts the input signal into a voltage output. The first processing circuit provides a first control voltage to an output node of the filter according to the voltage output, wherein the first control voltage is derived from an alternating current (AC) component of the voltage output. The second processing circuit provides a second control voltage to the output node of the filter according to the voltage output, wherein the second control voltage is derived from applying DC level shift to a direct current (DC) component of the voltage output.