PLL Lock Detection Circuit With Adaptive Counting Period
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Solution Overview
Problem
Conventional locking detecting circuits for Phase Locked Loop (PLL) circuits are inefficient in quickly detecting locking, leading to delayed booting times in memory systems as they rely on fixed counting time periods, which do not adapt to the changing frequency of the PLL output signal.
Innovation Solution
A locking detecting circuit that adjusts the counting time period based on the difference between current and preceding counting values, repeatedly decreasing or increasing the time period until the difference falls below specific threshold values, allowing for quicker and more precise detection of PLL locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a fixed counting time period is used to detect PLL locking, then the detection method is simple, but the detection speed is slow and booting time is delayed
Solution Approach 1:
The patent applies the dynamics principle by making the counting time period variable rather than fixed. The period determination unit dynamically adjusts the counting time period based on the current operating state and frequency of the PLL circuit. This allows the detection system to adapt to changing conditions, achieving faster locking detection without requiring excessively long fixed time periods, thereby reducing overall booting time.
Solution Approach 2:
The patent implements feedback by continuously monitoring the output signal frequency of the PLL circuit and using this information to adjust the counting time period. The period determination unit receives frequency information from the PLL output and modifies the counting period accordingly, creating a closed-loop system that optimizes detection speed based on actual PLL behavior, thus reducing detection time and booting time.
2Adaptability or versatility
If a fixed counting time period is used, then the circuit operation is simple, but it cannot adapt to changing PLL output signal frequency
Solution Approach 1:
The patent makes the counting time period dynamic by introducing a period determination unit that automatically adjusts the period based on PLL output frequency. This dynamic adjustment mechanism enables the system to adapt to frequency changes without manual intervention or complex reconfiguration, achieving high adaptability while keeping the overall circuit structure relatively simple through automated control.
Solution Approach 2:
The patent applies self-service by enabling the period determination unit to automatically adjust the counting time period based on the PLL's own output frequency characteristics. The system uses its own operational parameters to self-regulate the detection process, eliminating the need for external control or complex configuration, thus achieving adaptability with minimal added complexity.
3Measurement precision
If the counting time period is extended to ensure accurate detection, then detection accuracy improves, but detection time increases
Solution Approach 1:
The patent resolves this contradiction by making the counting time period dynamic rather than statically long. The period determination unit adjusts the counting period based on real-time PLL frequency information, allowing the system to use shorter counting periods when the PLL is close to locking (maintaining accuracy) while reducing overall detection time. This dynamic approach ensures sufficient measurement precision without requiring extended detection time.
Solution Approach 2:
The patent changes the parameter of counting time period from a fixed value to a variable that adapts to PLL frequency conditions. By modifying this parameter dynamically based on frequency measurements, the system achieves accurate locking detection with appropriately adjusted counting periods, avoiding the need for consistently long counting intervals and thereby reducing total detection time while maintaining precision.
Data Source
AI summary
A locking detecting circuit of a Phase Locked Loop (PLL) circuit includes an output signal counter performing an output signal counting operation of counting an output signal of the PLL circuit during a counting time period, a period determiner performing a period changing operation of decreasing the counting time period until a difference between a current period counting value and a preceding period counting value becomes smaller than a threshold value, and a locking detector detecting a locking of the PLL circuit when the difference between the current period counting value and the preceding period counting value becomes smaller than the threshold value.