PLL Lock Detection Using Multi-Interval Clock Count Comparison
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Solution Overview
Problem
Conventional lock detectors for Phase Locked Loops (PLL) struggle to accurately and quickly detect the lock status due to unstable feedback clock signals, leading to erroneous detection and delayed activation of next stage circuits.
Innovation Solution
A lock detector system that compares counting values of reference and feedback clock signals during multiple intervals, outputting prelock signals during shorter intervals and a lock signal when both intervals confirm synchronization, allowing for timely and accurate detection of PLL lock status.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a long time period is used for counting comparison, then the lock status detection accuracy is improved, but the detection speed deteriorates
Solution Approach 1:
The detection time period is segmented into multiple sub-intervals. The lock detector compares counting values at different time points within the period (e.g., at time point 0, time point 1, and time point 2). By dividing the detection process into segments rather than using a single long period, the system achieves accurate lock status detection without requiring the entire long period to elapse, thus improving detection speed while maintaining accuracy.
2Reliability
If the feedback clock signal is unstable during startup, then the phase difference comparison method may produce erroneous lock detection, but extending the detection period delays circuit activation
Solution Approach 1:
The system performs preliminary detection actions at multiple time points within the detection period. By comparing counting values at intermediate time points (not just at the end of the full period), the lock detector can identify lock status earlier. This preliminary action approach allows the system to detect lock status reliably even when the feedback clock signal is initially unstable, without requiring the full extended detection period to complete before activating the next stage circuit.
3Speed
If phase difference comparison is used for lock detection, then the detection speed is improved, but the accuracy deteriorates due to jitter accumulation
Solution Approach 1:
The invention introduces counting value comparison as an intermediary method between direct phase difference measurement and long-period timing. By counting clock cycles and comparing the counts at different time points, the system indirectly determines phase relationship without directly measuring phase difference. This intermediary approach avoids the jitter accumulation problem of direct phase comparison while maintaining faster detection than long-period methods.
Data Source
AI summary
The present invention discloses a PLL, a lock detector thereof and a lock detection method. The lock detector includes: a first detecting unit, adapted to compare a counting value of a reference clock signal with a counting value of a feedback clock signal every first interval and output a valid first prelock signal when the counting value of the reference clock signal is equal to the counting value of the feedback clock signal; a second detecting unit, adapted to output a valid second prelock signal when the counting value of the reference clock signal is equal to the counting value of the feedback clock signal during a second interval which is at least two times higher than the first interval; a third detecting unit, adapted to output a valid lock signal if the first prelock signal output from the first detecting unit every first interval is valid and the second prelock signal output from the second detecting unit is valid during the second interval. The PLL, lock detector thereof and lock detection method can detect the lock state quickly and correctly.