PLL Lock-Time Measurement Using Real-Time Counter Sampling
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Solution Overview
Problem
Phase-locked loops (PLLs) in electronic devices face challenges in quickly locking during startup, and existing methods for measuring PLL performance parameters like lock time and ramp rate are costly and impractical for high-volume testing, especially in manufacturing settings where high-end oscilloscopes are not feasible.
Innovation Solution
A system and method utilizing a reference clock, counters, buffers, and a processor to sample and compute PLL performance parameters such as lock time and slope, allowing for automated and cost-effective testing of PLL circuits during wafer probe testing without the need for external high-end equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-end oscilloscopes and test equipment are used to measure PLL performance parameters, then measurement precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent creates a virtual oscilloscope by software-based sampling and processing of PLL output signals using existing counters and memory resources. Instead of using physical high-end oscilloscopes, the system copies the measurement functionality through digital signal processing, where the processor samples counter values and reconstructs frequency ramp characteristics software-based, eliminating the need for expensive external test equipment while maintaining measurement precision
Solution Approach 2:
The PLL circuit under test performs its own self-diagnosis and measurement using built-in counters, memory, and processor resources. The system uses its own internal resources (counters 1408/1410, memory 1404, processor 1402) to measure its own performance parameters without requiring external test equipment, enabling self-service measurement that reduces manufacturing complexity and cost
2Measurement precision
If high-end oscilloscopes are used for PLL testing, then measurement precision is improved, but productivity decreases due to high cost and infeasibility for high volume testing
Solution Approach 1:
The patent replaces expensive physical oscilloscopes with a software-based measurement system that uses existing low-cost digital resources (counters and memory) to achieve the same measurement precision. This virtual instrumentation approach enables high-volume automated testing by eliminating the bottleneck of expensive external equipment while maintaining accurate frequency ramp rate and lock time measurements through digital sampling and processing
Solution Approach 2:
The system uses inexpensive, readily available digital components (standard counters and memory resources already present in the PLL device) instead of expensive oscilloscopes. These cheap digital resources can be rapidly instantiated for each test device, enabling high-volume production testing without the cost constraints of traditional oscilloscope-based measurement systems
3Measurement precision
If external high-end test equipment is used, then measurement precision is improved, but ease of manufacture worsens due to cost and complexity
Solution Approach 1:
The PLL device measures its own performance parameters using built-in digital resources (counters 1408/1410, memory 1404, processor 1402) without requiring external test equipment. The system autonomously samples counter values, processes the data to determine frequency ramp rate and lock time, and outputs measurement results, dramatically simplifying the manufacturing test setup and enabling easy automation while maintaining precise measurements
Solution Approach 2:
The patent makes existing digital resources (counters and memory) perform multiple functions: they serve both the normal operational functions of the PLL circuit and the measurement function simultaneously. The counters count both for operational timing and for frequency measurement, and memory stores both operational data and measurement samples, eliminating the need for separate dedicated measurement equipment and simplifying manufacturing
Data Source
AI summary
A system to test a PLL circuit driven by a reference clock includes a first counter coupled to a reference clock output, a first buffer coupled to the first counter, a second counter coupled to a controlled-oscillator (CO) output of the PLL circuit, a second buffer coupled to the second counter, and a processor configured to compute a PLL lock time according to second count values in the second buffer, and to compute a PLL startup slope according to the first count values in the first buffer and the second count values in the second buffer. A method includes powering up a PLL circuit of a wafer, sampling count values of a reference clock and second count values of the PLL circuit and computing a PLL performance parameter according to the sampled count values in a buffer.