PLL Lock Detection for Stable Digital Processing Clocks
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Solution Overview
Problem
Existing phase-locked loops in digital operation systems require hundreds of microseconds to milliseconds to generate a stable oscillator clock signal, affecting the accuracy of digital signal processing.
Innovation Solution
A phase-locked loop circuit with a locking detection circuit that outputs a locking signal when the oscillator clock signal and reference clock signal are synchronous, utilizing a phase detector, charge pump, loop filter, and voltage-controlled oscillator to ensure synchronization and generate a stable oscillator clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase-locked loop is used to generate an oscillator clock signal, then the frequency and phase of the oscillator clock signal can track the reference clock signal, but the system requires hundreds of microseconds to milliseconds to generate a stable signal, affecting processing accuracy
Solution Approach 1:
The patent applies preliminary action by pre-generating a temporary oscillator clock signal before the phase-locked loop completes its locking process. This temporary signal allows the digital processing circuit to operate during the acquisition and tracking phases, eliminating the time delay while ensuring stability once locking is achieved. The switching circuit transitions from the temporary signal to the stabilized PLL output signal.
2Productivity
If the digital processing circuit uses an unstable oscillator clock signal, then processing can begin immediately, but the accuracy of the processing result is negatively affected
Solution Approach 1:
The patent applies dynamics by implementing a dynamic switching mechanism that transitions the digital processing circuit between two clock signal sources based on the locking status. During the transient phase, the circuit uses a temporary unstable signal for immediate processing, then dynamically switches to the stable PLL output signal when locking is detected, thereby optimizing both speed and accuracy throughout the operation.
Data Source
AI summary
Disclosed is a phase-locked loop circuit, including: a phase-locked loop, a locking detection circuit, an input end for inputting a reference clock signal, a first output end for outputting an oscillator clock signal, and a second output end for outputting a locking signal, wherein the phase-locked loop is configured to output the oscillator clock signal according to the reference clock signal and control the reference clock signal and the oscillator clock signal to be synchronous; and the locking detection circuit is configured to output the locking signal to the second output end when the oscillator clock signal and the reference clock signal are synchronous.