PLL Lock Detection Circuit With Stable Delay Under PVT Variations
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Solution Overview
Problem
Phase-locked loop (PLL) circuits face challenges in accurately detecting the lock state due to fluctuations in process-voltage-temperature (PVT) parameters and bias voltage variations, affecting the delay time and accuracy of lock detection.
Innovation Solution
A PLL circuit design incorporating a comparator, pulse generator, bias circuit, and delay circuit that stabilizes currents and maintains a constant reference current level, using NMOSFETs and PMOSFETs with current mirroring and a bias resistor to generate phase comparison signals and delay pulse signals, ensuring accurate lock detection regardless of power supply voltage fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional lock detection circuit is used, then the circuit structure is simple, but the delay time changes with bias voltage variations causing inaccurate lock state detection
Solution Approach 1:
The bias circuit dynamically adjusts the bias voltages applied to the delay circuit based on detected voltage variations. The circuit continuously monitors and compensates for PVT parameter changes by modifying bias conditions in real-time, ensuring stable delay time despite environmental fluctuations.
Solution Approach 2:
The invention changes the bias voltage parameters dynamically to compensate for PVT variations. By adjusting the bias voltage levels based on detected changes, the delay circuit maintains consistent timing characteristics across different operating conditions, resolving the accuracy issue without requiring a completely redesign of the detection logic.
2Ease of operation
If bias voltage is used in the delay circuit, then the circuit can operate, but the delay time varies with bias voltage changes reducing detection accuracy
Solution Approach 1:
The bias circuit implements a feedback mechanism that detects voltage variations and automatically adjusts the bias voltages applied to the delay circuit. This closed-loop control ensures that delay time remains stable by compensating for bias voltage changes, maintaining both operational capability and timing precision.
Solution Approach 2:
The bias circuit autonomously detects and compensates for its own voltage variations without external intervention. By self-monitoring and self-adjusting the bias conditions, the circuit maintains stable delay time while continuing to operate normally, eliminating the need for external calibration or manual adjustment.
Data Source
AI summary
A phase-locked loop circuit including a lock detector is provided comprising a delay circuit including a load capacitor, and a bias circuit configured to generate a constant reference current, wherein the load capacitor is charged or discharged with a current whose level is dependent upon the reference current.