PLL Loss-of-Lock Detection Using Pseudorandom Clock Sampling
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Solution Overview
Problem
Phase locked loop (PLL) frequency synthesizers face challenges in maintaining phase lock due to variations in supply voltage and temperature, leading to potential loss of lock, which existing detection methods struggle to accurately and reliably address, especially in all-digital systems with multiple PLLs.
Innovation Solution
A detection system utilizing a pseudorandom bit sequence generator and shift registers to sample and re-synchronize signals, with comparators and an alarm control unit to generate a flag signal for loss of lock detection between PLL reference and feedback clock signals, ensuring accurate detection with minimal false alarms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional lock-detect circuit directly senses the control voltage of the VCO, then the detection accuracy is improved, but additional circuitry is inserted into the most sensitive node of the loop which increases device complexity and may affect stability
Solution Approach 1:
The patent introduces a pseudorandom bit sequence as an intermediary signal that is processed through shift registers and XOR gates to indirectly detect phase lock status. Instead of directly sensing the control voltage at the sensitive VCO node, the system uses this intermediary binary sequence that can be safely manipulated in the digital domain, thereby achieving detection without inserting complex circuitry into the analog core.
Solution Approach 2:
The patent replaces the analog voltage sensing mechanism with a digital signal processing approach. The control voltage sensing is substituted by processing a pseudorandom bit sequence through digital shift registers and comparators, transforming the detection mechanism from analog to digital domain, which simplifies the circuit and reduces sensitivity to analog noise.
2Device complexity
If loss of lock detection is implemented in digital domain outside the sensitive analog core, then device complexity is reduced and stability is improved, but detection precision may be compromised
Solution Approach 1:
The patent creates a digital copy of the phase relationship information through the pseudorandom bit sequence. The shift registers capture and hold binary representations of the phase states, allowing the digital domain to work with copies of the essential phase information without needing to directly measure the analog voltages, thus maintaining precision while operating in the simpler digital domain.
Solution Approach 2:
The patent transforms the continuous analog control voltage parameter into discrete binary parameters through the pseudorandom bit sequence generation and shift register sampling. This parameter transformation from continuous to discrete domain enables precise detection using digital logic while avoiding the complexities of analog sensing.
3Productivity
If multiple PLLs operate simultaneously in array arrangement, then system productivity is improved, but maintaining proper phase relation between array elements becomes more difficult increasing device complexity
Solution Approach 1:
The patent segments the phase relationship detection into independent parallel channels, with each PLL in the array having its own pseudorandom bit sequence generator and shift register set. This segmentation allows each PLL to be monitored independently while maintaining overall system productivity, and the modular structure actually reduces the complexity of managing phase relations across multiple units.
Data Source
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AI summary
With present invention, a detection system (S) and a detection method for detecting the loss of lock between a PLL reference clock signal (R) and a PLL feedback clock signal (F) are provided. Said detection system (S) comprises, pseudorandom bit sequence generator (1); first shift register (2a); second shift register (2b); third shift register (2c); first synchronizer (3a); second synchronizer (3b); third synchronizer (3c); first comparator (4a); second comparator (4b); and alarm control unit (5). Said method comprises the steps of, generating an n-bit wide pseudorandom bit sequence; sampling said sequence with PLL reference clock signal (R), PLL feedback clock signal (F) and inverse of PLL feedback clock signal (F); re-sampling and re-synchronizing said sampled sequences; comparing re-sampled and re-synchronized sequence, previously sampled with PLL reference clock signal (R), with re-sampled and re-synchronized sequences, previously sampled PLL feedback clock signal (F) and inverse of PLL feedback clock signal (F); generating a flag signal (6) if said comparisons give no match.