PLL Lock Detection Using Separate Phase and Frequency Indicators
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Solution Overview
Problem
Existing phase locked loops (PLLs) lack efficient methods to rapidly and accurately determine when they achieve phase and frequency lock, and to detect when they are out of lock, especially under conditions like temperature drift or unsuccessful tuning.
Innovation Solution
A lock detector system comprising a phase lock detector, frequency lock detector, and unlock detector, which uses loop filter parameters and timers to provide rapid and precise indications of phase and frequency lock, and detects cycle slips and settling periods to avoid false signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single lock detection method is used, then the detection is simple, but it cannot provide both rapid frequency lock indication and precise phase lock indication simultaneously
Solution Approach 1:
The lock detector is divided into two independent detection modules: a frequency lock detector that provides rapid frequency lock indication, and a phase lock detector that provides precise phase lock indication. This segmentation allows each module to be optimized for its specific function, achieving both fast response and high precision without compromise
2Measurement precision
If phase error threshold detection is used to determine phase lock, then phase lock can be detected, but false lock signals may occur during settling periods
Solution Approach 1:
The system determines settling periods in advance using loop filter parameter analysis, and uses this information to gate the phase lock detection output. By preparing the settling period status before phase lock detection is attempted, the system prevents false lock signals during transient periods while maintaining accurate phase lock detection during stable operation
3Measurement precision
If the lock detector is highly sensitive to detect small frequency offsets, then frequency lock detection precision is improved, but the detection time increases
Solution Approach 1:
The frequency lock detector uses loop filter parameter analysis to detect frequency lock conditions by monitoring parameters that change during the locking process. This approach allows the detector to identify frequency lock based on parameter convergence rather than requiring prolonged observation of small frequency offsets, thereby achieving both high precision and fast detection
Data Source
Figure 1~2
AI summary
A phase locked loop (100) is disclosed comprising: a phase detector (115), loop filter (120) and a frequency controlled oscillator (130). The phase detector (115) is configured to determine a phase difference (Δϕ) between a reference signal and a feedback signal (ϕv). The loop filter (120) is configured to perform a filtering operation on a signal derived from the phase difference (Δϕ) and to provide a control signal (PVT, ACQ, TR). The frequency controlled oscillator (130) is configured to receive the control signal (PVT, ACQ, TR) and provide an output signal with a frequency that varies according to the control signal (PVT, ACQ, TR). The phase locked loop (100) further comprises a lock detector (200), including: a phase lock detector configured to receive a first signal (Δϕ) from the phase locked loop (100), and to derive a phase lock signal (261) from the first signal (Δϕ), the phase lock signal (261) indicating whether the phase locked loop (100) is in phase lock; a frequency lock detector configured to receive a second signal (TR) from the phase locked loop (100), and to derive a frequency lock signal (262) from the second signal (TR), the frequency lock signal (262) indicating whether the phase locked loop (100) is in frequency lock. An unlock detector may be provided, configured to determine whether the first signal (Δϕ) has changed by a predetermined amount during a predetermined period.