Bang-Bang PLL Lock Detection Using Duty Cycle and Spectral Content
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing phase locked loops (PLLs) lack efficient methods to determine lock and unlock states, particularly in scenarios like tuners where accurate and timely detection is crucial for minimizing tuning time and preventing audio muting during reception.
Innovation Solution
A phase locked loop system incorporating a lock/unlock detector that utilizes a high pass filter, rectifier, low pass filter, and programmable gain elements to analyze the spectral characteristics and duty cycle of the binary phase error signal, with a timer and latch for reliable lock indication, allowing for improved detection of phase lock and unlock conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a phase locked loop uses a bang-bang mode phase detector to reduce complexity, then device complexity is reduced, but lock/unlock state detection precision deteriorates
Solution Approach 1:
The patent introduces a lock detector as an intermediary component that analyzes the binary phase error signal from the bang-bang phase detector. The lock detector uses a high-pass filter to extract spectral characteristics and a duty cycle detector to measure the proportion of high states, thereby enabling accurate lock state detection without requiring a complex linear mode phase detector.
2Productivity
If the PLL tuning time is reduced to improve productivity, then productivity is improved, but the reliability of lock detection may worsen
Solution Approach 1:
The lock detector operates continuously during the tuning process, performing preliminary analysis of the phase error signal characteristics. By monitoring spectral content and duty cycle in real-time, the system can reliably determine lock state even during rapid tuning transitions, ensuring accurate detection without requiring extended tuning time.
3Ease of operation
If audio muting is prevented during reception to improve ease of operation, then ease of operation is improved, but false lock detection may increase reducing reliability
Solution Approach 1:
The lock detector provides continuous feedback about the actual lock state by analyzing the phase error signal characteristics. This feedback mechanism allows the system to distinguish between true lock conditions and transient states, enabling continuous audio reception without muting while maintaining accurate lock detection through real-time monitoring of spectral and duty cycle parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables faster and more accurate detection of phase lock and unlock states, reducing tuning time and preventing audio muting, thereby enhancing reception quality in both analogue and digital reception schemes.
Implementation Method 1
The lock detector comprises a high pass filter configured to receive the phase error signal, and to pass high frequency content at the expected frequencies with which the bang-bang phase error will switch between its normalised limit values
Implementation Method 2
The lock detector comprises a rectifier for rectifying the output from the high pass filter
Implementation Method 3
The lock detector comprises a low pass filter arranged to receive a signal derived from the rectified signal
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
A phase locked loop (100) is disclosed comprising: a phase detector (104), a loop filter (108), a frequency controller oscillator (109) and a lock detector (150). The phase detector (104) is operable in a bang-bang mode to provide a binary phase error signal (Δϕ) indicating whether there is a positive or negative phase difference between a reference signal (ϕref) and a feedback signal (ϕfb). The loop filter (108) is configured to provide a control signal (TR) derived from the binary phase error signal (Δϕ). The frequency controlled oscillator (109) is configured to receive the control signal (TR) and provide an output signal (127) with a frequency that varies according to the control signal (TR). The lock/unlock detector (150) is configured to determine a lock/unlock state of the phase locked loop (100), the lock/unlock state derived from a duty cycle and/or spectral content of the binary phase error signal (Δϕ).