Dual-Edge PLL Lock Detection to Prevent False Lock Signals
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Solution Overview
Problem
Conventional phase locked loop (PLL) circuits face challenges in accurately and efficiently detecting when the PLL output has locked onto a reference signal, often resulting in false positive lock indications due to the instability of the PLL frequency during power-up and potential misalignment of reference and feedback signals.
Innovation Solution
A lock detector circuit utilizing dual edge-triggered flip flops and a timing circuit with a counter or firmware to detect phase alignment between a reference and a target signal, ensuring accurate lock detection by considering both rising and falling edges and resetting the timing operation when out of phase conditions are detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional lock detector compares reference and feedback signals using rising edge detection only, then the circuit complexity is reduced, but false positive lock indications occur due to PLL frequency instability during power-up
Solution Approach 1:
The lock detector is segmented into multiple independent detection paths: one path detects rising edges of the feedback signal, another path detects falling edges. Each path has its own flip-flop and comparison logic. This segmentation allows the circuit to comprehensively monitor both edges without increasing overall complexity, as each segment is simple but their combination provides robust lock detection that prevents false positives during PLL power-up instability.
2Reliability
If the lock detector waits for a longer period to confirm lock status, then false positive indications are reduced, but the time to achieve system operation increases
Solution Approach 1:
The circuit performs preliminary actions by continuously monitoring both rising and falling edges of the feedback signal throughout the PLL power-up sequence. The dual-edge detection mechanism is prepared in advance and actively tracks signal stability from the moment the PLL begins operating. When both edges show consistent phase relationship over a predetermined period, lock is immediately confirmed, avoiding unnecessary delays while preventing false positives through continuous preliminary monitoring.
3Measurement precision
If dual edge-triggered flip flops are used to detect both rising and falling edges, then lock detection accuracy is improved, but the device complexity increases
Solution Approach 1:
The circuit merges the functionality of rising-edge detection and falling-edge detection into a unified lock detection mechanism. Both dual-edge-triggered flip-flops operate simultaneously within the same circuit framework, sharing common components such as the reference signal input, the feedback signal input, and the final lock status output logic. This merging allows high-precision phase alignment detection through dual-edge monitoring while avoiding the complexity of completely separate detection circuits, as the paths are integrated and coordinated.
Data Source
AI summary
A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal.