PLL Lock-In Frequency Control Using Initial Phase Capture
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Solution Overview
Problem
Conventional Phase-Locked Loops (PLLs) face challenges in achieving fast lock-in, high accuracy, and low jitter due to random startup values and large phase errors, which hinder their ability to quickly synchronize with target frequencies.
Innovation Solution
The implementation of a PLL with a frequency comparator, phase predictor, and phase subtractor that captures initial phase and observes phase changes to quickly set the oscillator close to lock, using a search controller to find the appropriate oscillator control signal and filter parameters, thereby reducing errors and improving lock-in speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional PLL uses random startup values and standard phase accumulation, then the PLL can operate with simple circuitry, but the lock-in speed is slow and phase errors are large
Solution Approach 1:
The patent applies preliminary action by capturing the initial phase of the output clock signal before the PLL locking process begins. This initial phase value is stored and used to calculate an initial frequency estimate, allowing the PLL to start with informed parameters rather than random values. The phase predictor then uses this initial phase to generate predicted phase values that guide the locking process, significantly reducing lock-in time without requiring complex additional circuitry.
Solution Approach 2:
The patent replaces the traditional mechanical/analog phase accumulation process with a digital approach. Instead of relying on continuous analog integration, the system uses digital phase capture, initial frequency estimation, and phase prediction algorithms. This substitution enables faster computation and more precise control of the locking process, improving lock-in speed while maintaining circuit simplicity through digital implementation.
2Measurement precision
If conventional PLL waits for phase accumulation to determine frequency difference, then the measurement is accurate, but the lock-in time increases
Solution Approach 1:
The patent applies preliminary action by capturing the initial phase at the start of the locking process and using it to calculate an initial frequency estimate immediately. This eliminates the need to wait for extended phase accumulation to begin frequency measurements. The system performs preliminary frequency estimation using the captured initial phase and reference clock frequency, providing an early indication of the frequency difference that guides subsequent locking actions.
Solution Approach 2:
The patent implements dynamics by adapting the measurement approach based on the locking stage. During the initial phase, the system uses rapid frequency estimation based on captured phase values. As the PLL approaches lock, the system transitions to more traditional phase accumulation methods for final precision. This dynamic adaptation allows the system to achieve both fast initial response and accurate final measurement.
3Adaptability or versatility
If the PLL uses a wide frequency range for the controlled oscillator, then the PLL can cover more target frequencies, but the frequency resolution and accuracy decrease
Solution Approach 1:
The patent applies dynamics by making the oscillator control code adjustable based on the target frequency. The system captures the initial phase, estimates the initial frequency, and then determines the appropriate oscillator control code to achieve the desired target frequency. This dynamic adjustment allows the PLL to maintain high frequency resolution across a wide frequency range by optimizing the control parameters for each specific target frequency rather than using a fixed wide-range setting.
Solution Approach 2:
The patent changes parameters dynamically during the locking process. The initial frequency estimate derived from captured phase values is used to determine appropriate oscillator control codes. The system adjusts the oscillator control code based on the estimated frequency and target frequency requirements, enabling the PLL to maintain high resolution across different frequency ranges by adapting the control parameters rather than relying on a fixed configuration.
4Manufacturing precision
If the PLL uses traditional phase accumulation without initial phase capture, then the circuit is simple, but large phase errors occur during lock-in
Solution Approach 1:
The patent applies preliminary action by capturing the initial phase of the output clock signal before the locking process begins. This captured initial phase is used to calculate an initial frequency estimate and to initialize the phase predictor. By performing this preliminary phase capture and calculation, the system eliminates large phase errors that would otherwise occur during the lock-in process, achieving high phase accuracy without requiring complex additional circuitry beyond the initial phase capture mechanism.
Data Source
AI summary
A PLL has a frequency comparator that is active during lock-in. It outputs a signal related to the difference between the oscillator frequency and a target frequency. It captures an initial phase and observes change in phase relative to the initial phase. Two ways of capturing the initial phase are provided. The frequency comparator can provide input signals for the loop filter and make the PLL act as a frequency-locked loop during lock-in. Alternatively, it can provide input signals for a search controller that may perform a binary or other search. The frequency comparator may wait one or more cycles of the reference clock signal to reduce noise, or it may set a threshold to eliminate some noise. It may signal that the oscillator frequency equals the target frequency when the threshold has not been exceeded after a timeout. The search controller may directly or indirectly control the PLL's oscillator.