Semiconductor Clock Lock Control for Fast PLL Locking and Low Jitter
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Solution Overview
Problem
Phase locked loops (PLLs) face challenges in achieving high-speed locking while minimizing jitter propagation in semiconductor integrated circuits, as enhanced followability to the input reference signal's phase leads to increased jitter propagation in the output signal.
Innovation Solution
A semiconductor integrated circuit configuration that includes a first oscillation circuit, a second oscillation circuit, a detection circuit, a determination circuit, and a control circuit, which detects frequency differences and adjusts the control signal to reduce frequency differences during locking and increase them after locking is established, thereby achieving high-speed locking and reducing jitter propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If followability to the phase of the input reference signal is enhanced to lock phase synchronization at high speed, then locking speed is improved, but jitter propagation to the output signal increases
Solution Approach 1:
The patent applies dynamics by making the frequency difference adjustment value variable based on the locking state. During the locking process, a first adjustment value is used to achieve fast locking, and after locking is achieved, a second adjustment value is applied to reduce jitter propagation. This dynamic adjustment of parameters based on system state resolves the contradiction between fast locking and jitter reduction.
Solution Approach 2:
The patent implements periodic action through two distinct phases: a first period for fast locking with one frequency difference adjustment strategy, and a second period for jitter reduction with a different adjustment strategy. This periodic switching of control modes allows the system to achieve both high-speed locking and low jitter propagation at different times in the operation cycle.
Data Source
AI summary
In a semiconductor integrated circuit, a first oscillation circuit receives a first clock signal and outputs a second clock signal synchronized with the first clock signal in frequency and phase. A second oscillation circuit receives a control signal and outputs a third clock signal having a frequency corresponding to the received control signal. A detection circuit detects a frequency difference between the second clock signal and the third clock signal. A determination circuit determines whether a frequency locked state is established between the first clock signal and the second clock signal. A control circuit varies the control signal, such that the frequency difference decreases while the frequency locked state has not been established and increases after the frequency locked state is established.