PLL Loss-of-Lock Detection Using Pseudorandom Sequence Comparison
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Solution Overview
Problem
Phase locked loop (PLL) frequency synthesizers face challenges in maintaining phase lock due to supply voltage and temperature variations, leading to potential loss of lock, which is difficult to detect accurately without additional circuitry and can cause operational issues in systems with multiple PLLs.
Innovation Solution
A detection system using a pseudorandom bit sequence generator and shift registers to sample and synchronize signals, with comparators and an alarm control unit to generate a flag signal indicating loss of lock between the PLL reference and feedback clock signals, ensuring accurate detection without additional analog circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional lock-detect circuit directly senses the control voltage of the VCO, then the detection accuracy is improved, but additional circuitry is inserted into the most sensitive node of the loop
Solution Approach 1:
The patent introduces a pseudorandom bit sequence as an intermediary signal that is processed through shift registers and synchronizers. This mediator allows indirect detection of phase lock status by comparing processed versions of the pseudorandom sequence, avoiding direct sensing at the sensitive VCO control node while maintaining detection accuracy
Solution Approach 2:
The patent creates multiple copies of the pseudorandom bit sequence and processes them through different paths (one path through the PLL feedback loop, another path as reference). By comparing these copies after synchronization, the system can detect phase lock status without directly measuring the sensitive control voltage, thus avoiding additional circuitry at the critical node
2Device complexity
If digital domain loss of lock detector is used outside the sensitive analog core, then the device complexity is reduced, but the detection reliability may be affected
Solution Approach 1:
The patent replaces the conventional analog/direct sensing approach with a digital signal processing approach. By using digital pseudorandom sequence generation, shift register processing, and synchronous comparison, the system achieves reliable loss of lock detection in the digital domain outside the sensitive analog core, reducing circuitry complexity while maintaining detection reliability
Solution Approach 2:
The patent implements a feedback mechanism where the processed pseudorandom sequence from the PLL feedback path is continuously compared with the reference path. This continuous digital feedback comparison ensures reliable detection of phase lock status without requiring complex analog circuitry, maintaining detection reliability while simplifying the overall device structure
Data Source
AI summary
A detection system and a detection method for detecting the loss of lock between a PLL reference clock signal and a PLL feedback clock signal. The detection system includes a pseudorandom bit sequence generator; a first shift register; a second shift register; a third shift register; a first synchronizer; a second synchronizer; a third synchronizer; a first comparator; a second comparator; and an alarm control unit. The method comprises the steps of, generating an n-bit wide pseudorandom bit sequence; sampling the sequence with PLL reference clock signal, PLL feedback clock signal and inverse of PLL feedback clock signal; re-sampling and re-synchronizing the sampled sequences; comparing re-sampled and re-synchronized sequence, previously sampled with PLL reference clock signal, with re-sampled and re-synchronized sequences, previously sampled PLL feedback clock signal and inverse of PLL feedback clock signal; generating a flag signal if the comparisons give no match.