PLL Lock Detection Using Combined Lock and Out-of-Lock Circuits
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Solution Overview
Problem
In radar systems used for automotive adaptive cruise control, the phase-locked loop (PLL) must be reliably detected as either locked or out-of-lock to ensure accurate distance and speed measurements, posing a challenge due to the need for fast out-of-lock detection and precise lock detection, which are conflicting objectives.
Innovation Solution
A detector system comprising an out-of-lock detector circuit and a lock detector circuit, which receive a reference signal and a PLL oscillator signal, generate signals indicating out-of-lock and locked states, and are combined using a logic circuit to determine the PLL state, with the out-of-lock detector using pulse coincidence detection and the lock detector using pulse counting within a defined interval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single detection method is used for PLL state detection, then the device complexity is reduced, but the detection precision and speed cannot simultaneously satisfy both fast out-of-lock detection and precise lock detection
Solution Approach 1:
The patent divides the PLL state detection function into two separate detection circuits: an out-of-lock detector that quickly identifies out-of-lock states by detecting pulse coincidence, and a lock detector that precisely determines lock states by counting pulses within a time window. This segmentation allows each circuit to be optimized for its specific detection task, achieving both fast out-of-lock detection and precise lock detection without requiring a single complex detection system.
Solution Approach 2:
The patent combines the outputs of the out-of-lock detector and lock detector through a logic circuit to generate the final PLL state indication. The out-of-lock detector provides fast response for out-of-lock conditions, while the lock detector provides precise measurement for locked conditions. By merging these two detection results, the system achieves both speed and precision that would be difficult to obtain with a single detection method.
2Speed
If pulse coincidence detection is used for fast out-of-lock detection, then the detection speed is improved, but the detection precision for lock state is insufficient
Solution Approach 1:
The patent assigns different detection methods to different operational states: pulse coincidence detection is used specifically for fast out-of-lock detection, while pulse counting within a defined time window is used for precise lock state detection. This segmentation allows each method to be applied where it is most effective, achieving both fast response for out-of-lock conditions and precise measurement for locked conditions.
3Measurement precision
If pulse counting method is used for precise lock detection, then the detection precision is improved, but the detection speed is reduced
Solution Approach 1:
The patent segments the detection functionality so that pulse counting is used only for lock state detection where precision is critical, while out-of-lock detection uses the faster pulse coincidence method. This segmentation ensures that the slower but more precise pulse counting method is not applied to out-of-lock detection, thereby maintaining fast response times for critical out-of-lock conditions while achieving precise lock state measurement.
Data Source
AI summary
A detector for detecting a locked state and an out-of-lock state of a phase locked loop includes an out-of-lock detector circuit that receives a reference signal and an input signal representing a PLL oscillator signal. The out-of-lock detector detects an out-of-lock state of the PLL and generates an out-of-lock signal indicating whether an out-of-lock state is detected. The detector further includes a lock detector circuit that receives the reference signal and the input signal, detects a locked state of the PLL, and generates a lock signal indicating whether a locked state is detected. A logic circuit receives both the out-of-lock signal and the lock signal and combines both signals to obtain an output signal indicative of whether the PLL is in a locked state or an out-of-lock state.