PLL Lock Detection Using Phase and Frequency Error Thresholds
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Solution Overview
Problem
Existing Phase Locked Loop (PLL) systems face challenges in reliable and efficient lock detection due to reliance on zero crossing events, which can lead to extended detection times and erroneous results from either phase or frequency offset-based methods, especially when optimized for phase noise performance or affected by parasitic effects.
Innovation Solution
A PLL system that combines phase and frequency information for lock detection, using a phase detector and frequency comparator to generate a lock signal by comparing phase and frequency errors against threshold limits, ensuring stabilized phase and frequency outputs, thereby providing a more reliable and rapid detection method.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If phase offset-based lock detection is used, then phase noise performance is improved, but detection reliability deteriorates due to overshooting and ringing
Solution Approach 1:
The patent combines phase offset detection and frequency offset detection into a unified lock detection system. The phase detector generates phase error signals while the frequency comparator generates frequency error signals, and both are used together to determine lock status. This merging allows the system to benefit from phase noise performance while avoiding false locks caused by phase ringing, as the frequency condition provides additional verification that the phase error is not just temporarily zero due to oscillation.
Solution Approach 2:
The frequency comparator acts as an intermediary verification mechanism. Instead of relying solely on phase error signals, the system introduces frequency offset detection as an intermediate check. The lock detector uses both phase and frequency information, where the frequency comparator provides a mediating confirmation that helps distinguish between genuine lock and temporary phase zero-crossings during ringing.
2Loss of time
If frequency offset-based lock detection is used, then detection speed is improved, but reliability deteriorates due to parasitic effects causing false locks
Solution Approach 1:
The patent merges frequency offset detection with phase offset detection to create a more reliable lock detection system. While frequency-based detection provides faster response, combining it with phase-based detection allows the system to verify that frequency settling is accompanied by proper phase alignment, thereby preventing false locks caused by parasitic effects that might temporarily satisfy frequency conditions alone.
Solution Approach 2:
The system uses feedback from both the phase detector and frequency comparator to continuously monitor lock status. The lock detector receives feedback signals from both sources and only declares lock when both conditions are satisfied. This dual-feedback mechanism provides stronger verification than frequency-only detection, eliminating false positives while maintaining the speed advantage of frequency-based detection.
3Device complexity
If zero crossing event-based detection is used, then implementation simplicity is improved, but detection time increases due to required settling delays
Solution Approach 1:
The system performs preliminary frequency offset detection and comparison before final lock determination. The frequency comparator continuously monitors frequency error and prepares frequency error signals in advance, allowing the lock detector to make faster decisions without requiring extended settling delays after zero crossing events. This preliminary action reduces the mandatory waiting time while maintaining detection accuracy.
Solution Approach 2:
The patent implements dynamic lock detection that adapts to PLL behavior without requiring fixed settling delays. Instead of waiting for a predetermined time after zero crossing, the system dynamically evaluates both phase and frequency error signals in real-time, allowing lock detection to occur as soon as both conditions are satisfied. This dynamic approach eliminates arbitrary delay requirements while keeping the implementation relatively simple.
Data Source
AI summary
A method for Phase Locked Loop (PLL) lock detection includes determining a phase error by comparing a feedback phase to a reference phase. A frequency error is determined by comparing a feedback frequency to a reference frequency. A lock signal is determined in response to the phase error being less than an upper phase threshold and greater than a lower phase threshold, and the frequency error being less than an upper frequency threshold and greater than a lower frequency threshold.