PLL Lock Detection Circuit With Adjustable Phase Error Tolerance
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Solution Overview
Problem
Conventional lock detection circuits for phase locked loop systems fail to accurately distinguish between locked and unlocked states due to element mismatching, process variation, and temperature, often misconstruing minor static phase errors, and lack flexibility in adjusting phase error tolerance.
Innovation Solution
A lock detection circuit incorporating a delay unit and asserting logic unit, with a selection device to adjust phase error tolerance, includes an input clock error detection logic unit, sampling logic unit, and counting logic unit to generate phase error signals and unlock indicating signals, allowing for adaptable phase error tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional lock detection circuits are used, then the circuit structure is simple, but the detection accuracy is poor due to element mismatching and temperature variations
Solution Approach 1:
The patent implements dynamic phase error tolerance adjustment by introducing a selection device that can switch between different tolerance thresholds based on operating conditions. The circuit transitions from a fixed tolerance approach to a dynamic one that adapts to temperature variations and element mismatching, thereby improving detection accuracy without requiring complete circuit redesign
Solution Approach 2:
The patent changes the parameter of phase error tolerance from a fixed value to an adjustable parameter. By introducing multiple tolerance thresholds (first threshold and second threshold) and a selection device, the system can adapt the tolerance parameter according to actual operating conditions, resolving the contradiction between simple structure and accurate detection
2Adaptability or versatility
If fixed phase error tolerance is used, then the circuit operation is simple, but the adaptability to different applications is poor
Solution Approach 1:
The patent makes the phase error tolerance dynamic by introducing a selection device that can switch between different tolerance levels. This allows the circuit to adapt to different application requirements (first application using first threshold, second application using second threshold) without requiring multiple separate circuits, thus improving adaptability with controlled complexity increase
Solution Approach 2:
The patent creates a universal lock detection circuit that can serve multiple applications with different phase error tolerance requirements. The selection device enables a single circuit structure to function in multiple modes, providing both first threshold and second threshold capabilities, thereby achieving multi-functionality without proportionally increasing complexity
3Reliability
If conventional XOR gate and one-shoot counter are used, then the circuit is simple, but it cannot distinguish between locked and unlocked states accurately under process variation
Solution Approach 1:
The patent improves reliability by changing the detection parameter from a fixed phase error threshold to an adjustable threshold system. The selection device allows the circuit to select appropriate thresholds based on process variation conditions, enabling accurate distinction between locked and unlocked states even when element characteristics vary, thereby enhancing detection reliability
Solution Approach 2:
The patent implements a feedback mechanism where the selection device monitors operating conditions and adjusts the phase error tolerance threshold accordingly. This feedback loop ensures that the detection circuit maintains high reliability under varying process conditions by continuously adapting the threshold parameter based on actual system state
Data Source
AI summary
A lock detection circuit and method are disclosed for phase locked loop (PLL) systems. The lock detection circuit primarily includes a delay unit and an asserting logic unit. The delay unit receives the phase error signal of the PLL and produces a present phase error signal, and then accordingly generates at least one delayed phase error signal. The asserting logic unit generates an unlock indicating signal (UNLOCK) according to the present phase error signal and the delayed phase error signal. A phase lock indicating signal will be asserted if the unlock indicating signal is not asserted within a predetermined number of counting pulses.