PLL Digital Lock Detection Using Transition Time Windows
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional lock detectors for phase-locked loops face challenges in precision due to variations in capacitors and resistors caused by process, temperature, and power supply voltage, leading to instability and inaccurate lock indications.
Innovation Solution
A digital lock detector comprising a match detector and an arbiter that checks for transitions within a predetermined time window, generating match or un-match signals based on successive transitions, with a judge controller sampling lead and lag logic states to determine lock or unlock states, thereby improving precision and reducing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog circuits including capacitors and resistors are used in lock detectors, then the lock detection function can be implemented, but the precision and stability deteriorate due to variations caused by process, temperature and power supply voltage
Solution Approach 1:
The patent replaces the analog lock detector circuit (which uses capacitors and resistors susceptible to environmental variations) with a digital lock detector implemented using digital logic circuits. This substitution eliminates the sensitivity to process, temperature and voltage variations that plagues analog implementations, thereby improving both reliability and measurement precision simultaneously.
2Measurement precision
If a predetermined time window is constructed with lead and lag clocks to detect transitions, then the lock precision is improved, but the device complexity increases due to additional sampling circuits
Solution Approach 1:
The patent segments the clock transition detection process into distinct time intervals by introducing lead and lag sampled clocks. The lead sampler captures the state of the second clock at a lead time before the first clock transition, while the lag sampler captures it at a lag time after. This segmentation creates a predetermined time window for accurate transition detection, improving lock precision through temporal division of the detection process.
Solution Approach 2:
The patent performs preliminary sampling of the second clock state at lead time before the actual transition detection point. By capturing the clock state in advance (at time T - Δt/2) and comparing it with the lag-sampled state (at time T + Δt/2), the system prepares the necessary data for accurate transition detection within the predetermined time window, thereby improving measurement precision.
Data Source
AI summary
A digital lock detector for a phase-locked loop. The PLL generates a feedback clock according to a reference clock. The digital lock detector includes a match detector and an arbiter. When a first clock transitions, the match detector checks that whether a second clock transitions in a predetermined time window or not. The match detector generates a match signal if the second clock transitions in the predetermined time window. The arbiter counts a number of the successive match signals and generates a lock signal to indicate a lock state when the number exceeds a first predetermined number.