PLL Lock Detection Circuit for Faster Two-Stage Acquisition
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Solution Overview
Problem
Conventional Phase-Locked Loops (PLLs) experience prolonged locking times, especially at lower reference frequencies, which can be undesirable when the phase of the output signal is substantially offset from the reference frequency signal.
Innovation Solution
The implementation of a phase lock loop circuit that includes a voltage-controlled oscillator, a frequency divider, a switched capacitive circuit, and a secondary feedback circuit, which allows for two modes of operation: coarse locking using the VCO frequency and fine locking using the reference frequency, reducing the overall locking time by initializing the control voltage and dynamically adjusting it to achieve phase lock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional charge current pumping is used through a feedback loop, then the PLL can achieve phase lock, but the locking time becomes excessively long at lower reference frequencies
Solution Approach 1:
The patent segments the locking process into two distinct phases: a first locking mode using a first charge control circuit to achieve initial phase alignment, and a second locking mode using a second charge control circuit to achieve final precise lock. This segmentation allows each circuit to be optimized for its specific function, with the first circuit providing rapid initial locking independent of reference frequency and the second circuit providing precise final locking using the reference frequency signal.
Solution Approach 2:
The patent implements dynamic switching between two different charge control circuits based on the locking state. A detection circuit monitors whether phase lock has been achieved and dynamically couples either the first or second charge control circuit to the capacitor, allowing the system to adapt its behavior based on the current locking progress and minimize overall locking time.
2Speed
If the reference frequency is lowered, then the PLL operates at the desired frequency, but the activation/deactivation of the charge current pump occurs less frequently increasing locking time
Solution Approach 1:
The first charge control circuit performs preliminary action by rapidly adjusting the capacitor voltage to bring the VCO frequency close to the target frequency before the second charge control circuit takes over. This preliminary adjustment reduces the initial phase offset and gets the system close to lock condition much faster than waiting for the low-frequency reference signal to naturally guide the locking process.
Solution Approach 2:
The first charge control circuit acts as an intermediary that bridges the gap between the initial state and the final locked state. It provides the rapid initial adjustments needed to get close to lock, after which the second charge control circuit and reference frequency signal take over for precise final locking, combining the benefits of both fast response and frequency accuracy.
Data Source
AI summary
A phase lock loop (PLL) circuit incorporates switched capacitive circuitry and feedback circuitry to reduce the time to achieve a lock condition. During a first mode, the frequency of a voltage controlled oscillator (VCO) is used to adjust the control voltage of the VCO to achieve a coarse lock condition. During a second mode, a reference frequency is used to control a charge pump to more precisely adjust the control voltage to achieve fine lock of the PLL. Because the VCO frequency is significantly higher than the reference frequency, the control voltage is varied at a greater rate during the first mode. In some embodiments, the time to achieve lock may be further reduced by initializing the VCO control voltage to a particular voltage so as to reduce the difference between the control voltage at start-up and the control voltage at the beginning of the first mode during coarse lock.