PLL Coarse Lock Reduction Using Voltage Clamps and Split LPF Capacitors
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Solution Overview
Problem
The existing Phase Locked Loop (PLL) systems experience increased coarse lock time when changing coarse codes, which affects overall system performance by prolonging the settling time during frequency selection.
Innovation Solution
The implementation of switchable voltage clamps to control voltage transients in the Automatic Bank Calibration (ABC) current Digital to Analog Converter (DAC) and dividing the loop filter capacitor into two segments to minimize settling time, thereby reducing coarse lock time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the coarse code is changed in the frequency synthesizer, then the target frequency can be selected from a broader range, but the coarse lock time increases significantly
Solution Approach 1:
The patent applies preliminary action by pre-charging the loop filter capacitor through pull-up and pull-down switches before the coarse code change takes effect. This prepares the voltage at the DAC output in advance, so when the coarse code switches, the capacitor is already charged to the appropriate voltage level, eliminating the need for lengthy charging/discharging transients and significantly reducing coarse lock time.
Solution Approach 2:
The patent implements dynamics by making the loop filter capacitor charging/discharging paths dynamically controllable through switchable pull-up and pull-down switches. These switches are controlled by the coarse code change detection circuit, which activates the appropriate charging path only when needed, transforming a static filter into a dynamic system that adapts its behavior based on operational requirements.
2Measurement precision
If the loop filter capacitor is made larger to improve filtering performance, then the frequency selection accuracy improves, but the settling time increases
Solution Approach 1:
The patent applies preliminary action by pre-charging the loop filter capacitor to the target voltage level before the frequency switching occurs. This eliminates the need for the capacitor to charge from zero or a different voltage level after switching, thereby maintaining accurate frequency selection with a larger capacitor value while avoiding the associated increased settling time.
Solution Approach 2:
The patent changes the voltage parameter of the loop filter capacitor dynamically by controlling the pull-up and pull-down switches. When a coarse code change is detected, the appropriate switch is activated to rapidly adjust the capacitor voltage to the new required level, allowing the system to maintain high filtering accuracy with fast settling by dynamically changing the voltage parameter rather than relying on passive charging.
Data Source
AI summary
Some example embodiments herein disclose an electronic apparatus and method for reducing or minimizing coarse lock time of Phase Locked Loop (PLL). The method includes controlling a voltage transient in the ABC current DAC of the PLL using the plurality of switchable voltage clamps, where the ABC current DAC includes a plurality of MOSFETs. Further, the method includes dividing the loop filter capacitor of the PLL into two segments to reduce the LPF settling time. Further, the method includes minimizing or reducing the coarse lock time of the PLL using the controlled voltage transients and the divided loop filter capacitor.