PLL Lock Window Sampling for Faster Phase-Lock Calibration
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Solution Overview
Problem
Conventional phase-locked loop (PLL) circuits face delays during frequency calibration and phase-lock detection due to initial phase-offsets, which affect performance and energy consumption, particularly in mobile devices.
Innovation Solution
A method and device for PLL calibration that generate a lock window signal based on feedback signals, sample this signal at significant edges of a reference signal, and estimate frequency offset from consecutive active samples, updating the local oscillator and aborting calibration if phase offset exceeds predefined limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional phase-matching processes are used to achieve frequency calibration and phase-lock detection, then the PLL can achieve stable output frequency, but inherent delays occur due to initial phase-offset
Solution Approach 1:
The patent applies preliminary action by performing frequency calibration before phase-lock detection. The system first calibrates the VCO frequency to match the reference frequency, then performs phase-lock detection. This sequential approach eliminates the inherent delays caused by simultaneous phase-matching processes, as the frequency is pre-aligned before phase comparison begins.
Solution Approach 2:
The patent segments the phase-matching process into two distinct phases: frequency calibration phase and phase-lock detection phase. By dividing the originally simultaneous process into sequential segments, the system eliminates timing conflicts and phase-offset delays that occur when both operations attempt to occur concurrently.
2Measurement precision
If conventional phase-matching processes are used to determine frequency relationship, then frequency calibration can be performed, but overall energy consumption increases
Solution Approach 1:
The patent applies the skipping principle by rapidly transitioning through the frequency calibration process. The system uses a charge pump to quickly adjust the VCO frequency to match the reference frequency, then immediately proceeds to phase-lock detection. This rushed-through approach minimizes the time spent in high-power calibration mode, thereby reducing overall energy consumption while maintaining calibration accuracy.
3Adaptability or versatility
If conventional PLL circuits perform frequency calibration and phase-lock detection simultaneously, then comprehensive control is achieved, but collective delays affect other devices relying on PLL accuracy
Solution Approach 1:
The patent applies preliminary action by completing frequency calibration before initiating phase-lock detection. This ensures that the VCO frequency is already aligned with the reference frequency before phase comparison begins, eliminating delays that would otherwise propagate to other devices relying on PLL accuracy. The sequential approach maintains comprehensive control while preventing collective delays.
Data Source
AI summary
A system and method of calibrating a phase-locked loop (PLL) having at least a phase detector, a frequency divider and a local oscillator are provided. The disclosed example includes generating a lock window signal based on a feedback signal generated by the frequency divider where the lock window signal may form an active lock window relative to each significant edge of the feedback signal, generating a sampled window signal based on samples of the lock window signal at each significant edge of a reference signal, and estimating a phase offset between the reference signal and the feedback signal based on a number of consecutive samples of the sampled window signal that are active.