Gear-Shifting PLL Loop Filter for Fast Locking and Low Noise
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Solution Overview
Problem
Existing fast-locking phase-locked loops (PLLs) face challenges in achieving rapid locking operations without compromising noise-related performance, often requiring increased circuit area and current consumption due to the need for larger charge pump unit cells.
Innovation Solution
Implementing a gear-shifting loop filter with dynamic resistance and capacitance switching to control bandwidth, allowing for faster locking speeds without significant increases in cost or noise performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the charge pump current is increased to accelerate locking operation, then locking speed is improved, but noise-related performance deteriorates and circuit area increases
Solution Approach 1:
The loop filter bandwidth is made dynamically adjustable through gear-shifting mechanism. During acquisition phase, the bandwidth is switched to a wider configuration (first bandwidth) to enable faster locking. During tracking phase, the bandwidth is switched to a narrower configuration (second bandwidth) to improve noise performance. This dynamic adjustment resolves the contradiction between locking speed and noise performance without requiring increased charge pump current.
2Speed
If the charge pump current is increased to accelerate locking operation, then locking speed is improved, but circuit area and current consumption increase
Solution Approach 1:
The invention uses dynamic bandwidth switching through gear-shifting loop filter to achieve fast locking without increasing charge pump current magnitude. The bandwidth adjustment is accomplished by switching between different resistor and capacitor configurations in the loop filter, which are already present in the circuit. This approach achieves fast locking speed without requiring additional large charge pump unit cells, thereby avoiding increased circuit area.
3Speed
If the charge pump current is dynamically switched to improve locking speed, then locking operation is accelerated, but additional circuit complexity is introduced
Solution Approach 1:
The loop filter incorporates gear-shifting switches that can configure the R and C elements into different bandwidth configurations. During acquisition, the switches connect the loop filter in a first configuration with wider bandwidth. During tracking, the switches reconfigure the loop filter to a second configuration with narrower bandwidth. This uses existing circuit elements with dynamic reconfiguration rather than adding separate charge pump current switching mechanisms, thereby reducing additional circuit complexity.
Data Source
AI summary
A fast-locking phase-locked loop (PLL) and an associated fast-locking method thereof are provided. The fast-locking PLL may include a gear-shifting loop filter, which is configured to have a dynamic bandwidth. The gear-shifting loop filter may include a resistor set and a capacitor set coupled to the resistor set, where the resistor set is configured to have a dynamic resistance, and the capacitor set is configured to have a dynamic capacitance. More particularly, the dynamic resistance is switched from a first resistance to a second resistance and the dynamic capacitance is switched from a first capacitance to a second capacitance, to make the dynamic bandwidth be switched from a first bandwidth to a second bandwidth.