PLL Loop Filter Topology for High-Gain Low-Noise Phase Detection
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Solution Overview
Problem
High gain phase detector techniques for phase-locked loops (PLLs) are sensitive to process and temperature variations, supply noise, and limited supply voltage, which degrades PLL jitter performance and phase noise at low frequency offsets.
Innovation Solution
A PLL analog loop filter structure with a passive feedforward path and a lossy integrating path using opamp circuits with both inverting and non-inverting gains to reduce supply noise, combined with a digital-to-time converter to minimize quantization errors, and charge pump techniques to enhance PD gain and reduce sensitivity to supply noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If slope-based sampling PD structure is used to achieve high gain, then phase detector gain is improved, but process and temperature sensitivity increases
Solution Approach 1:
The patent changes the operating parameters of the phase detector by using a charge pump mechanism with controlled current sources instead of slope-based sampling. This allows the gain to be determined by current magnitudes rather than voltage slopes, making it less sensitive to process and temperature variations while maintaining high gain through controlled current levels.
Solution Approach 2:
The patent replaces the voltage-based slope sampling mechanism with a current-based charge pump mechanism. This substitution changes the fundamental operating principle from voltage slope detection to charge accumulation, which provides more stable gain characteristics across process and temperature variations.
2Reliability
If Up/Dn RC charging circuits are used to achieve PT-robust gain, then process and temperature sensitivity is reduced, but supply voltage limitation increases
Solution Approach 1:
The patent implements dynamic current control in the charge pump, allowing the current magnitudes to be adjusted based on operating conditions. This dynamic adjustment enables the system to maintain PT-robust gain while optimizing supply voltage utilization, as the current levels can be scaled to match available voltage headroom.
Solution Approach 2:
The patent changes from fixed RC time constants to dynamically controllable current sources. This allows the gain to remain PT-robust while the current levels can be optimized for different supply voltage conditions, effectively decoupling gain stability from supply voltage limitations.
3Measurement precision
If high gain phase detector techniques are used to reduce detector noise, then phase noise at low frequency offsets is improved, but supply noise sensitivity increases
Solution Approach 1:
The patent incorporates feedback mechanisms through the charge pump control logic that monitors and adjusts current levels to compensate for supply noise variations. This feedback approach allows the system to maintain high gain for low phase noise while actively rejecting supply noise through closed-loop control.
Solution Approach 2:
The patent introduces charge accumulation as an intermediary mechanism between the phase detector inputs and the output signal. This charge integration process acts as a natural low-pass filter that reduces the impact of high-frequency supply noise while preserving the low-frequency phase information needed for high precision measurement.
4Speed
If wide bandwidth is achieved through analog loop filter, then PLL bandwidth is improved, but noise from VCO and dividers increases
Solution Approach 1:
The patent uses periodic charging and discharging cycles in the charge pump to create a pulsed current waveform that, when filtered, produces a clean DC control voltage. This periodic action allows the system to achieve wide bandwidth by concentrating the control signal energy in specific frequency bands while filtering out broadband noise from VCO and dividers.
Solution Approach 2:
The patent maintains continuous charge accumulation on the loop filter capacitor, ensuring that the useful control signal is continuously updated without interruption. This continuous action allows wide bandwidth operation by ensuring that phase correction is applied without delay while the filtering process continuously rejects noise.
Data Source
AI summary
In described examples, a phase locked loop (PLL) has a first phase detector cell (PD) that has a gain polarity. The first PD cell has a phase error output and inputs coupled to a reference frequency signal and a feedback signal. A second PD cell has an opposite gain polarity. The second PD cell has a phase error output and inputs coupled to the reference frequency signal and the feedback signal. A loop filter has a feedforward path and a (lossy) integrating path coupled to an output of the filter. The feedforward path has a third PD cell that has phase error output AC-coupled to the filter output. The integrating path includes an opamp that has an inverting input coupled to the first PD cell phase error output and a non-inverting input coupled to the second PD cell phase error output.