PLL Loop Gain Feedback for Precise Bandwidth Calibration
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Solution Overview
Problem
Existing PLL circuits in mobile communication systems face challenges in calibrating loop bandwidth with high precision and speed, especially in integrated circuits, due to variations in element values and noise sensitivity, limiting their applicability to various types of PLLs and requiring large-scale circuits for calibration.
Innovation Solution
A phase locked loop circuit with a loop gain detecting circuit that includes a voltage-controlled oscillator, phase detector, charge pump, and loop filter, where the charge pump current is optimized based on measured loop gain, allowing for precise and rapid calibration of loop bandwidth, and is applicable to various types of PLLs, including offset PLL transmitters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If loop bandwidth calibration is performed using conventional methods in integrated circuits, then the calibration can be implemented, but the precision and speed of calibration are limited due to variations in element values and noise sensitivity
Solution Approach 1:
The patent implements a feedback mechanism where the calibrated loop bandwidth information is fed back to adjust the charge pump current dynamically. This closed-loop feedback system continuously monitors and corrects for element value variations and noise, enabling high-precision calibration that adapts to changing conditions rather than relying on fixed conventional calibration values
Solution Approach 2:
The patent changes the operating parameters by dynamically adjusting the charge pump current based on measured loop gain and calibrated loop bandwidth. This parameter adjustment allows the system to optimize calibration precision by adapting to actual circuit conditions, overcoming the limitations of fixed element values in conventional integrated circuit calibration methods
2Measurement precision
If conventional calibration circuits are used, then calibration can be performed, but large-scale circuits are required which increase chip area and power dissipation
Solution Approach 1:
The patent merges the calibration circuit functionality with the existing PLL circuit components, particularly reusing the phase detector, charge pump, and loop filter for both signal processing and calibration functions. This integration eliminates the need for separate large-scale calibration circuits, achieving precise loop bandwidth calibration while minimizing additional chip area and power consumption
Solution Approach 2:
The patent implements multi-functionality where the charge pump circuit serves dual purposes: maintaining its primary function of phase error correction while simultaneously enabling loop bandwidth calibration through dynamic current adjustment. This universal usage of existing components provides calibration capability without requiring dedicated calibration hardware, thereby reducing overall circuit scale
3Adaptability or versatility
If conventional PLL circuits are used in mobile communication systems, then basic functionality is achieved, but they are sensitive to load variations and have limited applicability to various types of PLLs
Solution Approach 1:
The patent implements dynamic adaptation by continuously measuring loop gain and adjusting charge pump current based on real-time loop bandwidth calibration. This dynamic behavior allows the circuit to adapt to different PLL configurations and load conditions, providing both versatility across various PLL types and stable performance under varying loads through active compensation
Data Source
AI summary
A PLL circuit equipped with a loop gain detecting circuit that can suppress the change of the loop gain. When detecting the loop gain, the frequency of the input signal to the second input (IN-2) of the phase detector is first changed, and the response corresponding to the change is detected by the output of the voltage locked oscillator. The detection is performed by connecting the output of the voltage locked oscillator with the counter and connecting the output of the counter with the integrator. The phase locked loop characteristics are optimized by performing feedback for the detection result on the value of the charge pump current.