PLL Loop Sampler Circuit for Reference Clock Loss Holdover
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Solution Overview
Problem
Phase locked loops (PLLs) face instability when the reference clock signal is lost, causing the output clock signal to reduce to zero or a low frequency, which is undesirable for many applications.
Innovation Solution
A system comprising a clock detect circuit and a loop sampler circuit that continuously generates a clock detect signal to indicate the presence or loss of the reference clock, and stores control voltages from the PLL's loop filter to supply them back when the reference clock is lost, disabling the charge pump and maintaining a stable output signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PLL operates normally without additional circuits, then the device complexity is low, but the output signal becomes unstable when the reference clock is lost
Solution Approach 1:
The loop sampler circuit continuously samples and stores the control voltage from the loop filter while the reference clock is present, preparing the voltage in advance for use when the reference clock is lost. This preliminary action ensures that when signal loss occurs, the stored voltage can immediately stabilize the output without waiting for the PLL to relock.
Solution Approach 2:
The loop sampler circuit acts as an intermediary between the loop filter and the charge pump/PLL. It captures the control voltage from the loop filter and can supply it back to the charge pump or directly to the VCO when the reference clock is lost, mediating the transition and maintaining output stability during the interruption.
2Reliability
If the charge pump remains active during reference clock loss, then the PLL continues to operate, but the output frequency drifts to zero or low frequency
Solution Approach 1:
The system applies preliminary anti-action by disabling the charge pump when the reference clock is lost. This prevents the charge pump from generating erroneous control signals that would cause frequency drift. Simultaneously, the loop sampler circuit supplies the previously stored control voltage to maintain the VCO output frequency, counteracting the potential harmful effect of charge pump operation during reference loss.
3Ease of manufacture
If the PLL output frequency is allowed to drop to zero during reference loss, then the circuit operation is simple, but the application reliability is poor
Solution Approach 1:
The loop sampler circuit performs preliminary sampling of the control voltage during normal operation, storing it in advance on a capacitor. When the reference clock is lost, this pre-stored voltage is immediately supplied to the charge pump or VCO, maintaining the output frequency without requiring complex real-time adjustment mechanisms, thus preserving both simplicity and reliability.
Data Source
AI summary
Systems, methods, and apparatus for a circuit for synchronization of a reference signal and an output signal of a phased-lock loop (PLL) are disclosed. The method comprises continuously generating, by a clock detect circuit connected to the PLL, a clock detect signal indicating whether the reference signal of the PLL is present or lost. The method further comprises continuously sampling and storing, by a loop sampler circuit connected to the PLL, a voltage from a loop filter of the PLL, when the reference signal is present. In addition, the method comprises configuring a charge pump of the PLL into a high impedance state, thereby disabling the charge pump, when the clock detect signal indicates that the reference signal is lost. Further, the method comprises supplying the voltage to the PLL to maintain a frequency of the output signal of the PLL, when the reference signal is lost.