PLL Reference Loss Detection with Pseudo-Random Code Registers
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Solution Overview
Problem
Existing PLL clock generation systems face challenges in promptly detecting the loss of an input reference signal, leading to potential system malfunctions and data loss due to delayed detection and increased noise from ratiometric comparisons and separate clock domains.
Innovation Solution
A code-based loss detector circuit that generates unique codes each clock cycle, using a pseudo-random number generator and serially shifting codes through registers, allowing for early detection of input reference signal loss by comparing register values, thereby mitigating potential damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ratiometric comparison methods are used for reference signal loss detection, then detection capability is provided, but detection delay increases and noise is introduced
Solution Approach 1:
The patent extracts the detection function from the main PLL operation by using a separate code generator that operates independently. The code generator creates unique codes for each reference clock cycle, and these codes are stored in registers for comparison. This separation allows detection to occur without interfering with the main PLL timing operations, thereby reducing detection delay while maintaining reliability.
Solution Approach 2:
The patent implements preliminary action by pre-generating codes in registers before they are needed for comparison. The code generator continuously generates codes for each reference clock cycle, and these codes are stored in registers in advance. When loss detection is needed, the comparison can immediately occur between current and previous codes without waiting for signal accumulation, thus reducing detection delay.
2Adaptability or versatility
If separate clock domains are used for reference and PLL clocks, then independent operation is enabled, but noise and complexity increase
Solution Approach 1:
The patent introduces an intermediary mechanism - the code generator and code registers - that mediates between the reference clock domain and the PLL clock domain. Instead of directly comparing clocks from separate domains (which introduces noise), the system converts both into code representations that can be safely compared. The codes serve as an intermediary representation that eliminates direct domain interaction and its associated noise.
3Speed
If code-based detection with serial shifting is used, then detection speed increases to 2-3 clock cycles, but device complexity increases
Solution Approach 1:
The patent uses copying by creating multiple register copies of the same code value at different time instances. Instead of using complex comparison logic, the system simply copies the current code into a register and compares it with the previous code copy. This copying approach simplifies the detection logic while enabling rapid 2-3 clock cycle detection, as it avoids complex ratiometric calculations.
Data Source
AI summary
In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.