PLL Lost-Lock Detection Circuit for Automatic Power Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Electronic devices with Phase Locked Loop (PLL) circuits face challenges in automatically transitioning to a low power consumption state when the reference clock signal is stopped and maintaining this state until the clock is restarted, without requiring dedicated terminals or complex manual intervention.
Innovation Solution
The implementation of a mixed analog and digital circuitry system, including a phase frequency detector and a lost_lock detection circuit, which generates a lost_lock signal to control power consumption states, allowing the device to automatically transition to a low power state when the reference clock is not synchronized and return to normal when restarted.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a dedicated input terminal is used to control power-down state, then power management control is achieved, but device complexity increases
Solution Approach 1:
The PLL circuit automatically detects its own lock status through the lost_lock detection circuit and self-manages power states by transitioning to low power mode when unlocked, eliminating the need for external dedicated control terminals
Solution Approach 2:
The existing lock status detection mechanism is extended to serve dual purposes: both maintaining PLL operation control and managing power consumption states, allowing one circuit to perform multiple functions without adding dedicated power control terminals
2Use of energy by stationary object
If manual intervention is used to manage power states, then power consumption is controlled, but ease of operation deteriorates
Solution Approach 1:
The system automatically transitions to low power consumption state when the PLL loses lock detection, eliminating the need for manual intervention to manage power states while maintaining optimal energy efficiency
Solution Approach 2:
The lost_lock detection circuit continuously monitors the lock status and provides feedback to automatically control power state transitions, ensuring power consumption is optimized based on real-time operational status without user intervention
3Reliability
If the PLL circuit operates continuously, then operational reliability is maintained, but power consumption increases
Solution Approach 1:
The PLL circuit alternates between normal operation mode and low power consumption mode based on lock status, operating continuously only when needed and entering periodic low-power states when unlocked, balancing reliability with energy efficiency
Solution Approach 2:
The circuit changes its operational parameters by transitioning between different power consumption states based on the lock status, maintaining full operational parameters when locked and reducing to low-power parameters when unlocked
Data Source
AI summary
An apparatus and method for automatically transitioning the operation of an electronic device to a reduced power consumption state if an input reference clock signal is stopped or no longer synchronized (locked) with the operation of the electronic device. The electronic device is automatically returned to a normal operating/power consumption state if the reference clock is restarted. Mixed analog and digital electronic components are employed to handle the transition of the electronic device between reduced and normal power consumption states. These components can include a phase frequency detector and a lost_lock detection circuit. The lost_lock detection circuit is typically connected to the output of phase frequency detector and outputs a lost_lock signal if the reference clock signal has stopped or lost_lock with a feedback clock signal. The lost_lock detection circuit operates on at least one error signal outputted by the phase frequency detector and is relatively insensitive to variations in the duty cycle of the reference and feedback clock signals.